Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2001-03-30
2003-06-03
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S787000
Reexamination Certificate
active
06574766
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a turbo decoding apparatus and interleave-deinterleave apparatus suitable for use in, for example, a communication system such as a mobile communication system.
BACKGROUND ART
In a conventional wireless communication field including a mobile communication or the like, a device of interleaver and corresponding deinterleaver are introduced to sort the data series in order to make a burst error, which tends to occur frequently at a particular portion of the data series, corrected more easily. That is, a transmitting signal is transmitted after interleaved by an interleaver on the transmitting side, and received on the receiving side, and then the signal is deinterleaved by a deinterleaver.
A conventional interleaver and deinterleaver will hereinafter be described.
FIG.
6
(A) is a block diagram showing an arrangement of a conventional interleaver. As shown in FIG.
6
(A), an interleaver
100
comprises an interleave RAM
101
, a writing counter
102
, a reading counter
103
and a reading address converting circuit
104
. The interleaver
100
shown in
FIG. 6
(A) is arranged based on an assumption that the interleaver interleaves an input data series composed of 24×16=384 pieces of data (D
000
, D
001
, D
002
, . . . , D
383
) (i.e., the interleaver size=24×16).
In this case, the interleave RAM
101
(hereinafter denoted simply as “RAM
101
”) is a unit for storing therein the input data series (D
000
, D
001
, D
002
, . . . , D
383
) for interleave operation. The writing counter
102
is a unit for counting the numbers from 0 to 383 sequentially and outputs the counted value as a writing address (A
000
, A
001
, A
002
, . . . , A
383
) for the RAM
101
. Thus, the input data series are sequentially written in the RAM
101
at addresses from A
000
to A
383
in accordance with the writing address (A
000
to A
383
).
The reading counter
103
is a unit for counting a series of numbers from 0 to 383 for generating the reading address for the RAM
101
. The reading address converting circuit
104
is a unit for effecting an arithmetic operation expressed by x*16(mod383) on the counted number x (=0 to 383) supplied from the reading counter
103
, thereby converting the series of counted numbers x generated from the reading counter
103
into one having a regular interval of 16. Thus, the series of reading addresses supplied to the RAM
101
becomes a series of addresses having a regular interval of 16 such that A
000
, A
016
, A
032
, . . . , A
368
, A
001
, A
017
, A
033
, . . . , An*16(mod
383
), . . . , A
351
, A
367
, A
383
.
If the interleaver
100
is arranged as described above, as shown in FIG.
6
(B), when data is written into the memory, the counted value of the writing counter
102
directly serves as the writing address and the input data series (D
000
, D
001
, B
002
, . . . , D
383
) are written at the corresponding address regions in the RAM
101
sequentially. On the other hand, when data are read from the memory, data are read from address regions designated by the reading address which are generated at the regular interval of 16 from the reading address converting circuit
104
.
In this way, the input data series (D
000
, D
001
, B
002
, . . . , D
383
) are interleaved, and as a result outputted like D
016
, D
032
, . . . , D
368
, D
001
, D
017
, D
033
, . . . , Dn*16(mod
383
), . . . , D
351
, D
367
, D
383
.
In other words, the interleave operation carried out in the present interleaver
100
can be illustrated as shown in
FIG. 7
, for example. That is, when data pieces of 24×16=384 are written into the RAM
101
, the written data are arrayed in the direction indicated by an arrow A in this order while when the same data pieces are read from the memory, data pieces arrayed in the direction indicated by an arrow B are read in this order, whereby the interleave operation is accomplished (this manner of interleave operation is known as block interleave).
Meanwhile, FIG.
8
(A) is a block diagram showing an arrangement of a conventional deinterleaver. As shown in FIG.
8
(A), the deinterleaver
200
comprises a deinterleave RAM
201
, a writing counter
202
, a reading counter
203
and a reading address converting circuit
204
. The deinterleaver
200
shown in FIG.
8
(A) is arranged based on an assumption that the deinterleaver deals with an input data series composed of 16×24=384 pieces of data (D
000
, D
001
, B
002
, . . . , D
383
).
In this case, the deinterleave RAM
201
(hereinafter denoted simply as “RAM
201
”) is a unit for storing therein the input data series (D
000
, D
001
, B
002
, . . . , D
383
) for interleave operation. The writing counter
202
is a unit for counting the numbers from 0 to 383 sequentially and outputs the counted value as a writing address (A
000
, A
001
, A
002
, . . . , A
383
) for the RAM
201
. Thus, the input data series are sequentially written in the RAM
201
at addresses from A
000
to A
383
in accordance with the writing address (A
000
to A
383
).
The reading counter
203
is a unit for counting a series of numbers from 0 to 383 for generating the reading address for the RAM
201
. The reading address converting circuit
204
is a unit for effecting an arithmetic operation expressed by x*24(mod
383
) on the counted number x (=0 to 383) supplied from the reading counter
203
, thereby converting the series of counted numbers x generated from the reading counter
203
comes to have a regular interval of 24. Thus, the series of reading addresses supplied to the RAM
201
becomes a series of addresses having a regular interval of 24 such that A
000
, A
024
, A
048
, . . . , A
360
, A
001
, A
002
, . . . , An*24(mod
383
), . . . , A
335
, A
359
, A
383
.
If the interleaver
200
is arranged as described above, as shown in FIG.
8
(B), when data is written into the memory, the counted value of the writing counter
202
directly serves as the writing address and the input data series (D
000
, D
001
, B
002
, . . . , D
383
) are written in the RAM
201
at the corresponding address regions sequentially. On the other hand, when data are read from the memory, data are read from address regions designated by the reading address which are generated at the regular interval of 24 from the reading address converting circuit
204
.
In this way, the input data series (D
000
, D
001
, B
002
, . . . , D
383
) are interleaved and as a result, outputted like D
000
, D
024
, D
048
, . . . , D
360
, D
001
, D
025
, . . . , Dn*24(mod
383
), . . . , D
335
, D
359
, D
383
. In other words, the operation of the present interleaver
200
is equivalent to an interleave operation at a size of 16×24. That is, as for example shown in
FIG. 9
, when data pieces of 16×24=384 are written into the RAM
201
, the written data are arrayed in the direction indicated by an arrow A in this order while when the same data pieces are read from the memory, data pieces arrayed in the direction indicated by an arrow B are read in this order.
Accordingly, if the input data series are interleaved by 24×16 in the above-described interleaver
100
, and the resulting output data series (D
000
, D
016
, D
032
, . . . , D
368
, D
001
, D
017
, D
033
, . . . , Dn*16(mod
383
), . . . , D
351
, D
367
, D
383
) are supplied to the present deinterleaver
200
, then writing and reading data series are carried out as shown in FIG.
8
(C). That is, when writing is carried out, the output data series are written in the RAM
202
in the aforesaid order sequentially and when reading is carried out, data series are read at a regular interval of 24 addresses. As a result, the output data series are restored as one before the interleave operation (i.e., deinterleave operation is effected).
Meanwhile, recently, a new error correcting system known as “turbo encoding and turbo decoding” comes to be utilized. According to a communication system having the system of turbo encoding and turbo decoding applied thereto, transmitting information is encod
Kawabata Kazuo
Nakamura Takaharu
Obuchi Kazuhisa
Yano Tetsuya
Baker Stephen M.
Fujitsu Limited
Katten Muchin Zavis & Rosenman
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