Turbo decoder control for use with a programmable...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S786000

Reexamination Certificate

active

06516437

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to error-correction coding and, more particularly, to a decoder for parallel convolutional codes, i.e., turbo codes.
A new class of forward error control codes, referred to as turbo codes, offers significant coding gain for power limited communication channels. Turbo codes are generated using two recursive systematic encoders operating on different orderings of the same information bits. A subset of the code bits of each encoder is transmitted in order to maintain bandwidth efficiency. Turbo decoding involves an iterative algorithm in which probability estimates of the information bits that are derived for one of the codes are fed back to a probability estimator for the other code. Each iteration of processing generally increases the reliability of the probability estimates. This process continues, alternately decoding the two code words until the probability estimates can be used to make reliable decisions.
The maximum a posteriori (MAP) type algorithm introduced by Bahl, Cocke, Jelinek, and Raviv in “Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate”,
IEEE Transactions on Infonnation Theory,
March 1974, pp. 284-287, is particularly useful as a component decoder in decoding parallel concatenated convolutional codes, i.e., turbo codes. The MAP algorithm is used in the turbo decoder to generate a posteriori probability estimates of the systematic bits in the code word. These probability estimates are used as a priori symbol probabilities for the second MAP decoder. Three fundamental terms in the MAP algorithm are the forward and backward state probability functions (the alpha and beta functions, respectively) and the a posteriori transition probabilities (the sigma function).
It is desirable to provide a control and data handling structure for a turbo decoder which allows for a programmable interleaver, variable block length, and multiple code rates.
BRIEF SUMMARY OF THE INVENTION
A control for a turbo decoder utilizing a MAP decoding algorithm comprises an address generator for addressing systematic data symbols, parity data symbols, and systematic likelihood ratios according to a pre-determined memory mapping. A control signal indicates which of a plurality of component code words comprising a turbo code word is being decoded, each employing the same memory mapping. The systematic data symbol values are accessed in the order required by the alpha, beta and gamma functions of the MAP decoding algorithm such that interleaving and de-interleaving functions in the MAP decoding algorithm are performed in real-time, i.e., without delay. The systematic symbol and parity symbol contributions to the gamma function of the MAP decoding algorithm are computed in parallel using parallel channel transition probability look-up tables, such that the channel transition probabilities required in the gamma calculations are accessed at the same rate as the likelihood ratios. This memory-mapping in combination with other data handling functions (e.g., multiplexing, combinatorial logic and parallel processing) minimizes memory requirements for the turbo decoder and enables the use of programmable interleavers, variable block lengths, and multiple code rates.


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“A Viterbi Algorithm with Soft-Decision Outputs and its Applications,” Joachim Hagenauer; Peter Hoeher; IEEE 1989, pp. 1680-1686.

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