Turbo decoder architecture with mini-trellis SISO

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S780000, C714S792000

Reexamination Certificate

active

06976203

ABSTRACT:
The Turbo decoding architecture has a first soft-input soft-output (SISO) device having a complex trellis structure and a Turbo decoder loop with a second SISO device having a simpler trellis structure. Coded information from a channel is processed by the first SISO device to generate a soft-output based on the coded information. The soft-output is then processed in an iterative loop using the second SISO device. The second SISO device interacts with a decoder device to produce a value representative of the transmitted information.

REFERENCES:
patent: 5812601 (1998-09-01), Schramm
patent: 6112326 (2000-08-01), Khayrallah
patent: 6556633 (2003-04-01), Brianti et al.
patent: 1 137 002 (2001-09-01), None
Hoeher, P., et al., “Iterative Decoding/Demodulation of Coded DPSK Systems”, IEEE GLOBECOM 98, Nov. 1998, pp. 598-603.
Souvignier, T., et al., “Turbo Decoding for PR4: Parallel Versus Serial Concatenation”, IEEE ICC 99, Jun. 1999, pp. 1638-1642.
May, T., et al., “Turbo Decoding of Convolutional Codes in Differentially Modulated OFDM Transmission Systems”, IEEE 49th Vehicular Technology Conference, Jul. 1999, pp. 1891-1895.
Oberg, M., et al., “Parity Check Codes for Partial Response Channels”, IEEE GLOBECOM 99, Dec. 199, pp. 717-722.
Divsalar, D., et al., “Serial Concatenated Trellis Coded Modulation with Rate-1 Inner Code”, IEEE GLOBECOM 2000, Nov. 2000, pp. 777-782.
“Reduced Complexity In-Phase/Quadrature-Phase Turbo Equalisation Using Iterative Channel Estimation”, B.L. Yeap, et al., 0-7803-7097-1/01 IEEE, 2001.
“A Soft-Input Soft-Output Maximum A Posteriori (MAP) Module to Decode Parallel and Serial Concatenated Codes”, S. Benedetto, et al.,TDA Progress Report42-127, Nov. 15, 1996.
“Convergence Properties of Iterative Decoders Working at BIT and Symbol Level”, B. Scanavino, et al. Politecnico de Torino, Torino, Italy.
“VLSI Architectures for Turbo Codes”, Guido Masera, et al.,IEEE Transactions on Very Large Scale Integration(VLSI)Systems, vol. 7, No. 3, Sep. 1999.
“SCTCM with Inner Rate-1 Accumulate Code” (printed slide presentation), Hugo M. Tullberg and Paul H. Siegel, Signal Transmisson and Recording Group, UCLA, Jan. 30, 2002.
“Serial Concatenated Trellis Coded Modulation with Inner Rate-1 Accumulate Code”, Hugo M. Tullgerg and Paul H. Siegel. 0-7803-7208-5/01 IEEE, 2001.
“On Joint Iterative Decoding of Variable-length Source Codes and Channel Codes”, Ahmadreza Hedayat and Aria Nosratinia, Multimedia Communications Laboratory, Richardson, TX.
“Trellis Turbo-Codes in Flat Rayleigh Fading with Diversity”, Christos Komninakis and Richard D. Wesel, 0-7803-7206-9/01 IEEE, 2001.
“A Low Latency SISO with Application to Broadband Turbo Decoding”, Peter A. Beerel and Keith M. Chugg,IEEE Journal on Selected Areas in Communications, vol. 19, No. 5, May 2001.
“Further Results on a Reduced-Complexity, Highly Power-/Bandwidth-Efficient Coded Feher-Patented Quadrature-Phase-Shift-Keying System with Iterative Decoding”, M.K. Simon and D. Divsalar,IPN Progress Report42-146, Aug. 15, 2001.
“A Soft-Input Soft-Output APP Module for Iterative Decoding of Concatenated Codes”, S. Benedetto, et al.,IEEE Communications Letters, vol. 1, No. 1, Jan. 1997.
William E. Ryan, Concatenated Codes for Class IV Partial Response, IEEE Transactions On Communications, vol. 49., No. 3, Mar. 2001, pp. 445-454.
Joachim Hagenauer, Iterative Decoding of Binary Block and Convolutional Codes, IEEE Transactions On Information Theory, vol. 42, No. 2, Mar. 1996, pp. 429-445.
D. Divsalar and F. Pollara, Multiple Turbo Codes for Deep-Space Communications, TDA Progress Report 42-121, May 15, 1995, pp. 66-77.
Tom V. Souvignier, Turbo Decoding for Partial Response Channels, IEEE Transactions On Communications, vol. 48, No. 8, Aug. 2000, pp. 1297-1307.
Divsalar et al.,Serial Concatenated Trellis Coded Modulation with Rate-1 Inner Code, Dec. 2000, pp. 777-782.
Souvignier et al.,Turbo Decoding for PR4: Parallel Versus Serial Concatenation, Jun. 1999; pp. 1638-1642.
May et al.,Turbo Decoding of Convolutional, Codes in Differentially Modulated OFDM Transmission Systems, Jul. 1999, pp. 1891-1895.
Öberg et al.,Parity Check Codes for Partial Response Channels, 1999, pp. 717-722.
Hoeher et al.,Iterative Decoding/Demodulation of coded DPSK systems, 1998, pp. 598-603.

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