Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-03-28
2006-03-28
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S795000, C714S791000, C714S794000
Reexamination Certificate
active
07020832
ABSTRACT:
The present invention relates to a turbo decoder having a state metric, a calculating method using the turbo decoder and a computer-readable recoding medium for executing a calculation method implemented to the turbo decoder. The turbo decoder includes branch metric calculation unit, state metric calculation unit and log likelihood ratio calculation unit. The present invention may reduce calculation steps by simplifying a conventional turbo decode algorithm, reducing a size of a hardware, which the turbo decoder can be implemented in as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). The present invention can be implemented in an error correction in wireless communication system and satellite communication system.
REFERENCES:
patent: 6343368 (2002-01-01), Lerzer
patent: 6381728 (2002-04-01), Kang
patent: 6434203 (2002-08-01), Halter
patent: 6658071 (2003-12-01), Cheng
“Implementation and Performance of a Serial MAP Decoder for use in Iterative Turbo Decoder”, S. Pictrobon, Satellite Communications Research Centre, Univ of S. Australia, 1 page.
Cho Han Jin
Jeon In San
Kim Hyuk
Kim Kyung Soo
Kim Whan Woo
Abraham Esaw
Blakely & Sokoloff, Taylor & Zafman
De'cady Albert
Electronics and Telecommunications Research Institute
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