Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-03-01
2005-03-01
Chase, Shelly A (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S701000
Reexamination Certificate
active
06862707
ABSTRACT:
A turbo code encoder with an interleaver having two recursive systematic constituent code (RSC) encoders. The encoder encodes a finite sequence of informative bits without requiring a plurality of tail bits to flush the registers of each encoder to an all-zero state. The interleaver reduces the turbo code overhead by using only a single tail bit sequence. The interleaver also selectively reorders integers in accordance with a predefined set of rules.
REFERENCES:
patent: 6334197 (2001-12-01), Eroz et al.
Divsalar et al., Turbo codes for PCS applications, 1995, IEEE, p. 54-59.*
Blackert et al., Turbo code termination and interleaver conditions, Nov. 23, 1995, IEEE Elect. Lett. vol. 31, No. 24, p. 2082-2084.*
Barbulescu et al., Terminating the trellis of turbo codes in the same state, Jan. 5, 1995, IEEE, Elect. Lett., vol. 31, No. 1, p. 22-23.*
Olsen, D, A hybrid interleaving scheme that enables packet switching on multiple-access radion communication channels, Dec. 1999, IEEE Trans. on Comm., vol. 47, No. 12, p. 1777-1780.*
Wang et al., On the performance of turbo codes, 1998, IEEE, p. 987-992.
Chase Shelly A
InterDigital Technology Corporation
Volpe and Koenig PC
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