Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Tunneling through region of reduced conductivity
Patent
1998-02-02
2000-05-02
Munson, Gene M.
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Tunneling through region of reduced conductivity
257 30, H01L 2906
Patent
active
060575565
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates in general to methods for producing functional elements of nanoelectronics and computer facilities, more specifically it concerns tunnel-effect devices and can find application for producing single-electron logic gates, single-electron memory circuits and sensors operable at room temperature.
BACKGROUND ART
Fundamentals of modern theory of correlated electronic tunneling have been elaborated as early as several years ago. A worldwide interest displayed in this new domain of physics and technology is concerned with the broadest potentialities and prospects offered by further research in single-electron phenomena and development of new promising technologies based thereon.
From the standpoint of physics the meaning of that phenomenon resides in electronic correlations due to Coulomb electrostatic interaction of electrons in diverse micro- and nano-scale structures. On the other hand, single-electronics is a route towards development of such electronic device that the operating concept of which is based on information coding by lone electrons.
One state-of-the-art three-lead (three-electrode) semiconductor device (U.S. Pat. No. 4,286,275) is known to comprise a combination of the base region having a physical size of the order of the length of a free path of the majority carrier, the emitter region which establishes a first barrier relative to the base region and featuring the barrier width sufficient for quantum-mechanical tunneling, and the collector base forming a lower barrier With respect to the base region than the first barrier and featuring the barrier width high enough to inhibit quantum-mechanical tunneling and ohmic contact with each of the emitter, base, and collector regions.
The three-lead (three-electrode) semiconductor device under discussion featuring a changeover time of about 10-12 s and offering a negative dynamic resistance, is created from a thin barrier region in the emitter section having a barrier height exceeding that in a wider barrier region of the collector section which separated by the base section having a width comparable with the length of the length of a free path of the majority carrier. The operation of the device is based on quantum-mechanical tunneling as the principal mechanism of electrical conduction through the base region to the collector region.
Field of application: amplification, changing-over, and establishing dynamic resistance.
Specific features: the collector barrier has such a width that tunneling current flowing therethrough is but negligible. Emitter-base junction: main conductance due to quantum-mechanical tunneling.
Dimensions: base--100 .ANG.;
width of emitter barrier--80 .ANG.;
width of collector barrier--120 to 150 .ANG..
The device discussed before is based on quantum-mechanical tunneling as the principal mechanism of electrical conduction from the emitter region to the base region, and of transferring hot major carriers through the base region to the collector region.
One more state-of-the-art three-lead (three-electrode) semiconductor device based on quantum wells (U.S. Pat. No. 4,912,531) is known to function as a MOS transistor. This means that in a general sense the three leads of the device may be considered as a source, a pass, and a drain. The output terminal communicates, by virtue of the tunneling effect, with a number of parallel circuits of quantum wells, each of which is adequately small for the energy levels therein to quantize discretely. In each of such pit circuits the second pit is connected to a second common conductor, while the first pit is electronically connected to a first common conductor.
A method for making GaAs-based electric elements of nanoelectronics and computer facilities with an insulating molecular Langmuir-Blodgett layer (U.S. Pat. No. 5,079,179) is known to comprise formation of an insulating layer appearing as Langmuir-Blodgett (LB) film interposed between a GaAs substrate and the conducting terminal.
The thickness of said layer is variable so as to set the functi
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Gubin Sergei Pavlovich
Khanin Vladimir Viktorovich
Khomutov Genadii Borisovich
Kolesov Vladimir Vladimirovich
Soldatov Evgenii Sergeevich
Munson Gene M.
Samsung Electronics Co,. Ltd.
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