Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2002-03-21
2004-12-21
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S029000, C710S062000, C710S066000, C710S313000
Reexamination Certificate
active
06834319
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer system input/output (I/O) nodes and, more particularly, to transaction handling in a tunnel device for an I/O node.
2. Description of the Related Art
In a typical computer system, one or more processors may communicate with input/output (I/O) devices over one or more buses. In addition those processors may communicate with each other through an additional bus or buses. In many cases, these buses are shared buses.
Unfortunately, many shared bus systems suffer from drawbacks. For example, multiple devices attached to a bus may present a relatively large electrical capacitance to devices driving signals on the bus. In addition, the multiple attach points on a shared bus produce signal reflections at high signal frequencies which reduce signal integrity. As a result, signal frequencies on the bus are generally kept relatively low in order to maintain signal integrity at an acceptable level. The relatively low signal frequencies reduce signal bandwidth, limiting the performance of devices attached to the bus. An example of a shared bus used by many systems is a front side bus (FSB), which may typically interconnect one or more processors and a system controller.
To overcome some of the drawbacks of a shared bus, some computers systems may use packet-based communications such as point-to-point links, for example, between devices or nodes. In such systems, nodes may communicate with each other by exchanging packets of information. In general, a “node” is a device which is capable of participating in transactions upon an interconnect. For example, the interconnect may be packet-based, and the node may be configured to receive and transmit packets. Generally speaking, a “packet” is a communication between two nodes: an initiating or “source” node which transmits the packet and a destination or “target” node which receives the packet. When a packet reaches the target node, the target node accepts the information conveyed by the packet and processes the information internally. A node located on a communication path between the source and target nodes may relay or forward the packet from the source node to the target node.
When some of these nodes forward a transaction, the transaction may be received into the forwarding node at one frequency and on a bus having a given width. The transaction may then be internally forwarded onto another bus or path having a different frequency and width before the transaction is finally forwarded onto a second external bus.
SUMMARY OF THE INVENTION
Various embodiments of a tunnel device for an input/output node of a computer system are disclosed. In one embodiment, a tunnel device includes a first interface, a second interface and a control unit. The first interface may be configured to receive a plurality of data bytes associated with a command packet on a first external input/output bus. The external input/output bus may be for example a packet bus compatible with HyperTransport™ technology. The second interface may be coupled to the first interface by an internal data path configured to convey up to a maximum number of data bytes in a given cycle. The second interface may also be configured to transmit the data bytes on a second external input/output bus. The control unit may be coupled to control the conveyance of the data bytes from the first interface to the second interface upon the internal data path. The first interface may be further configured to align the smaller number of data bytes on a corresponding number of designated bits of the internal data path with no intervening invalid data bytes when conveying a smaller number of data bytes than the maximum number of data bytes.
In one particular implementation, the maximum number of data byes may be 16 and may include four subsets of data bytes. The four subsets of data bytes may include a first subset of data bytes having a first fixed number of data bytes, a second subset of data bytes having a second fixed number of data bytes, a third subset of data bytes having a third fixed number of data bytes and a fourth subset of data bytes having a fourth fixed number of data bytes. The second subset of data bytes may include the first subset of data bytes. The third subset of data bytes may include the first subset of data bytes and the second subset of data bytes. Further, the fourth subset of data bytes may include the first subset of data bytes, the second subset of data bytes and the third subset of data bytes.
In another specific implementation, the first fixed number of data bytes may be four, the second fixed number of data bytes may be eight, the third fixed number of data bytes may be 12 and the fourth fixed number of data bytes may be 16.
In yet another specific implementation, the first interface may be further configured to transmit the first, second, third and the fourth subset of data bytes on the corresponding number of designated bits of the internal data path such that the first subset of data bytes may be aligned to the lowest order group of bits of the internal data path.
In still another specific implementation, the first interface may be further configured to transmit the first, second, third and the fourth subset of data bytes on the corresponding number of designated bits of the internal data path such that the first subset of data bytes may be aligned to the highest order group of bits of the internal data path.
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patent: 2003/0097514 (2003-05-01), Ennis et al.
“HyperTransport Technology I/O Link: A High-Bandwidth I/O Architecture” White Paper; Advanced Micro Devices, Inc.; Sunnyvale, CA; Jul. 20, 2001.
Advanced Micro Devices , Inc.
Auve Glenn A.
Curran Stephen J.
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
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