Tuning high-side and low-side CMOS data-paths in CML-to-CMOS...

Details Tuning high-side and low-side CMOS data-paths in CML-to-CMOS... Tuning high-side and low-side CMOS data-paths in CML-to-CMOS...

2011-04-19

2011-04-19

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Interface

Logic level shifting

C326S064000, C326S073000, C326S077000

Reexamination Certificate

active

07928765

ABSTRACT:
Electronic circuitry and techniques are disclosed for controlling one or more timing parameters associated with a circuit that converts a signal of a first type to a signal of a second type. For example, the converter circuit may convert a differential digital logic signal, such as a current mode logic (CML) signal, to a complementary metal oxide semiconductor (CMOS) signal. For example, apparatus for converting a first type of signal to a second type of signal comprises the following circuitry. First circuitry is configured for generating a first pair of CMOS signals in response to a differential digital logic signal, the first pair of CMOS signals comprising a first CMOS signal having a first polarity and a second CMOS signal having a second polarity. Second circuitry is configured for adjusting, with respect to the first pair of CMOS signals, a transition time of one of the first CMOS signal and the second CMOS signal relative to a transition time of another of the first CMOS signal and the second CMOS signal.

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