Tungsten silicide polycide gate electrode formed through stacked

Details Tungsten silicide polycide gate electrode formed through stacked Tungsten silicide polycide gate electrode formed through stacked

1996-04-29

1998-01-20

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257 64, 257 74, 257388, 257412, H01L 2976, H01L 2144

Patent

active

057104549

ABSTRACT:
A method for forming a tungsten silicide polycide gate electrode within a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and the tungsten silicide polycide gate electrode which is formed through the method. Formed upon a semiconductor substrate is a gate oxide layer. Formed upon the gate oxide layer is a first polysilicon layer which is formed through annealing a first amorphous silicon layer. Formed upon the first polysilicon layer is a second polysilicon layer which is formed through annealing a second amorphous silicon layer. Formed upon the second polysilicon layer is a tungsten silicide layer formed through a Chemical Vapor Deposition (CVD) method. The first polysilicon layer and the second polysilicon layer have a crystallite size no greater than about 0.3 microns, and the first polysilicon layer and the second polysilicon layer have a dopant concentration larger than about 1E16 atoms per cubic centimeter. Optionally, at least a third polysilicon layer may be added through annealing at least a third amorphous silicon layer between the second polysilicon layer and the tungsten silicide layer. Optionally, an fourth amorphous silicon layer may be added directly beneath the tungsten silicide layer.

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