Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-06-03
2002-04-02
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S643000, C438S683000, C438S655000
Reexamination Certificate
active
06365511
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to a semiconductor barrier and, more specifically, to a semiconductor barrier subjected to a high temperature deuterium anneal to improve hot carrier reliability.
BACKGROUND OF THE INVENTION
For simplicity of manufacture, a manufacturer would prefer to fill contact vias in semiconductor devices by depositing a metal layer, typically aluminum (Al) into the via and onto a patterned silicon substrate. However, during certain fabrication processes, the Al may diffuse into the silicon substrate, and vice versa. If the Al diffuses too far into the silicon substrate, an undesirable condition called junction spiking can occur. To prevent this diffusion, a barrier layer of titanium nitride (TiN) is deposited over the silicon substrate and before the Al is deposited. However, TiN does not adhere well to the silicon substrate. In contrast, titanium (Ti) adheres well to both the silicon substrate and TiN. Therefore, an adhesion layer of titanium (Ti) is first deposited on the silicon substrate, followed by a barrier layer of TiN.
After the Al is deposited, the metal stack is subjected to a low temperature metallization boost anneal at about 400° C. to 425° C. for between ½ and 2 hours. This annealing is typically carried out in a forming gas mixture of nitrogen (N
2
) and a low concentration of hydrogen (H
2
). Unfortunately, TiN begins to break down between about 425° C.-450° C. If the anneal is prolonged or performed at a temperature over about 425° C., the TiN barrier breakdown allows Ti to diffuse through the TiN layer and into the Al layer. This results in a large increase in the metal stack sheet resistance and via resistance. Also, there is an increased likelihood of junction leakage and, in the worst case, results in junction spiking.
It has been discovered that if sub-0.5 micron devices, e.g., CMOS, FLASH, bipolar, analog, are annealed in a forming mixture of deuterium (D
2
) instead of H
2
, hot carrier reliability results in a 100 times improvement. However, for annealing with a D
2
mixture to be effective, process temperatures should be above 400° C. Therefore, the process temperatures for D
2
annealing and the effective use of a TiN barrier are in direct conflict.
Accordingly, what is needed in the art is a barrier material suitable for use in high-temperature D
2
anneals conducted to improve hot carrier reliability.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a method of forming a metal stack structure over a substrate of a semiconductor device, comprising: (a) forming a first metal layer over the substrate, (b) forming a tungsten silicide nitride layer over the first metal layer, (c) forming a second metal layer over the tungsten silicide nitride layer, and (d) annealing the metal stack structure at a diffusion temperature. The tungsten silicide nitride layer inhibits diffusion of the metal in the metal stack. While this particular embodiment is directed to the use of a tungsten silicide nitride, it should be specifically understood that the present invention may include the use of other metal silicides, such as metals selected from Groups 5 or 6 of the Periodic Table.
In one particularly advantageous embodiment, the metal stack is formed in a contact opening or via of the semiconductor device. The first metal layer may be a stack layer of titanium and titanium nitride and the second metal layer may be aluminum. Alternatively, the stack layer may be tantalum and tantalum nitride and the second metal layer may be copper. However, other combinations of metal stacks and metals known to those skilled in the art may also be used.
In another aspect of the present invention, forming the tungsten silicide nitride layer includes forming the tungsten silicide nitride layer over a titanium nitride layer. In certain embodiments, the annealing time may be greater than about one-half hour and the annealing may be conducted at a temperature greater than about 400° C., and if desired, the annealing may be performed in the presence of a forming gas mixture comprising deuterium.
In an alternative embodiment, a titanium silicide layer may be formed over the substrate. However, the tungsten silicide nitride layer may also include forming the tungsten silicide nitride layer over the titanium silicide layer.
In one aspect of the present invention, the semiconductor device may be a CMOS device, a BiCMOS device, a FLASH device, an analog device, or a Bipolar device.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
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Kizilyalli Isik C.
Merchant Sailesh M.
Radosevich Joseph R.
Agere Systems Guardian Corp.
Bowers Charles
Nguyen Thanh
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