Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-06-03
2004-12-28
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S631000, C438S672000, C257S752000, C257S763000
Reexamination Certificate
active
06835649
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to tungsten stud layers, as employed within microelectronic fabrications. More particularly, the present invention relates to tungsten stud layers with enhanced reliability, as employed within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common within the art of microelectronic fabrication to employ when fabricating microelectronic fabrications conductor stud layers for purposes of both: (1) contact to contact regions within microelectronic fabrications; as well as (2) electrical interconnection between electrical interconnection layers within microelectronic fabrications. As is understood by a person skilled in the art, and although conductor stud layers may theoretically be formed from any of several conductor materials as are conventional in microelectronic fabrication, including but not limited to metal, metal alloy, doped polysilicon and polycide conductor materials, a particularly common conductor material for forming conductor stud layers within microelectronic fabrications is a tungsten conductor material. In turn, tungsten conductor materials are desirable for forming conductor stud layers within microelectronic fabrications since tungsten conductor materials are generally less susceptible to electromigration when forming conductor stud layers within microelectronic fabrications.
While conductor stud layers, and in particular tungsten stud layers, are thus desirable in the art of microelectronic fabrication and generally unavoidable in the art of microelectronic fabrication, conductor stud layers, and in particular tungsten stud layers, are nonetheless not entirely without problems in the art of microelectronic fabrication.
In that regard, conductor stud layers are often difficult to form with enhanced reliability within microelectronic fabrications.
It is thus desirable in the art of microelectronic fabrication to form within microelectronic fabrications conductor stud layers with enhanced reliability.
It is towards the foregoing object that the present invention is directed.
Various conductor stud layer structures and methods for fabrication thereof, and in particular tungsten stud layers and methods for fabrication thereof, having desirable properties, have been disclosed in the art of microelectronic fabrication.
Included among the conductor stud layer structures and methods for fabrication thereof, but not limited among the conductor stud layer structures and methods for fabrication thereof, are tungsten stud layer structures and methods for fabrication thereof disclosed within: (1) Shih et al., in U.S. Pat. No. 5,654,234 (a tungsten stud layer structure formed absent a void within a reentrant contact via by employing a two layer tungsten layer deposition method incorporating an anisotropic etchback of a first tungsten layer deposited within the two layer tungsten layer deposition method); (2) Huang et al., in U.S. Pat. No. 5,672,914 (a tungsten stud layer structure formed absent a dimple therein incident to being formed while employing a spin-on-glass (SOG) planarizing and subsequent etchback method); (3) Huang et al., in U.S. Pat. No. 5,747,379 (a tungsten stud layer structure formed absent a seam therein by employing a two layer tungsten layer deposition method incorporating an etchback of a first tungsten layer deposited within the two layer tungsten layer deposition method); and (4) Huang et al., in U.S. Pat. No. 5,874,355 (a tungsten stud layer structure formed absent a volcano shape by nitrogen plasma treating a titanium nitride barrier layer upon which is formed the tungsten stud layer structure).
Desirable in the art of microelectronic fabrication are additional methods and material which may be employed in the art of electronic fabrication for forming conductor stud layers, and in particular tungsten stud layers, with enhanced reliability.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for forming a tungsten stud layer within a microelectronic fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the tungsten stud layer is formed with enhanced reliability.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a microelectronic fabrication, and a microelectronic fabrication fabricated in accord with the method.
To practice the method of the present invention, there is first provided a substrate. There is then formed upon the substrate a patterned dielectric layer which defines a via. There is then formed over the substrate and filling the via a blanket tungsten layer. There is then etched back the blanket tungsten layer to form recessed within the via a tungsten stud layer. There is then formed over the substrate and filling a recess above the tungsten stud layer recessed within the via a blanket conductor capping layer formed of a conductor material other than tungsten. Finally, there is then planarized the blanket conductor capping layer to form within the via a patterned conductor capping layer formed upon the tungsten stud layer.
The method of the present invention contemplates a microelectronic fabrication fabricated in accord with the method of the present invention.
The present invention provides a method for forming a tungsten stud layer within a microelectronic fabrication, wherein the tungsten stud layer is formed with enhanced reliability.
The present invention realizes the foregoing object by forming a tungsten stud layer recessed within a via within a microelectronic fabrication, wherein there is formed upon the tungsten stud layer, and within a recess above the conductor stud layer within the via, a patterned conductor capping layer formed of a conductor capping material other than tungsten. By employing such a patterned conductor capping layer, contaminant materials entrapped within a seam or void formed within the tungsten stud layer may be sealed such as to provide enhanced reliability of the tungsten stud layer and a microelectronic fabrication within which is employed the tungsten stud layer.
The method of the present invention is readily commercially implemented.
The present invention employs methods and materials as are otherwise generally conventional in the art of microelectronic fabrication, but employed within the context of a specific process ordering and specific process limitations to provide a tungsten stud layer in accord with the present invention. Since it is thus at least in part a specific process ordering and a specific series of process limitations which provides at least in part the present invention, rather than the specific existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.
REFERENCES:
patent: 5654234 (1997-08-01), Shih et al.
patent: 5672914 (1997-09-01), Huang et al.
patent: 5747379 (1998-05-01), Huang et al.
patent: 5874355 (1999-02-01), Huang et al.
patent: 5895268 (1999-04-01), Mathews
patent: 6221754 (2001-04-01), Chiou et al.
patent: 6537912 (2003-03-01), Agarwal
patent: 6635528 (2003-10-01), Gilbert et al.
Chang Yu-Ching
Chien Wen-Chen
Fan Yu-Da
Lee Wei-Cheng
Liu Kuo-Yen
Malsawma Lex H.
Smith Matthew
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
LandOfFree
Tungsten plug with conductor capping layer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Tungsten plug with conductor capping layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Tungsten plug with conductor capping layer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3310523