Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-01-21
2001-08-14
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S712000
Reexamination Certificate
active
06274472
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication, and more particularly to a tungsten interconnect and methods of fabricating the same.
2. Description of the Related Art
Modern integrated circuits routinely contain millions of individual transistors and other electronic components. Most of the interconnections for the numerous individual transistors in a modern integrated circuit are provided via one or more metallization layers that serve as global interconnect levels. Each metallization layer is ordinarily deposited on the substrate of the integrated circuit as a single continuous layer that is thereafter patterned lithographically and etched to remove metal from areas where metal lines are not required.
In addition to the one or more metallization layers, modern integrated circuits also incorporate numerous routing-restricted interconnect levels commonly known as local interconnects. Local interconnects are used for short metallization runs such as those that locally interconnect gates and drains in NMOS and CMOS circuits and those that connect a given metallization layer to a particular structure in the integrated circuit.
A method frequently employed to form local interconnect structures involves a damascene process in which the substrate containing the integrated circuit is coated with a layer of dielectric material that is lithographically patterned and etched to form trenches in the dielectric layer where the local interconnect structures will be deposited. For example, a local interconnect structure intended to interconnect the source or drain of a transistor requires a trench to be formed in the overlying dielectric layer that extends down to the source or drain. Thereafter, a conducting contact or interconnect is formed in the trench.
Doped polysilicon and tungsten represent two conventionally used materials for global and local interconnect structures. Both materials have high melting points and thus alleviate many thermal budgeting problems associated with other commonly used conducting materials. Tungsten is frequently favored over polysilicon as its resistivity may be as much as one or more orders of magnitude lower than comparably sized doped polysilicon structures.
Despite the several advantages offered by tungsten as an interconnect material, the integration of tungsten into semiconductor processing involves a number of significant challenges. Tungsten exhibits poor adhesion to oxide. Accordingly, the conventional fabrication of a tungsten conducting structure in a trench in an oxide film requires an initial deposition of a barrier or adhesion layer on the oxide in advance of the tungsten deposition. The barrier layer material is selected to exhibit acceptable adhesion to the underlying oxide and the later-deposited tungsten film.
Titanium nitride is a common material used for a barrier layer, although other titanium based films, such as Ti:W have been used as well. In one conventional process, a thin film of titanium is deposited by physical sputtering. Thereafter a thin film of titanium nitride is deposited on the titanium by chemical vapor deposition (“CVD”).
In many conventional processes, the tungsten film is deposited by the CVD reduction of WF
6
in a silane ambient. In at least one conventional process, the barrier film is exposed to a flow of silane for short period. The initial flow of silane is stopped and thereafter the film is exposed to a simultaneous flow of silane, WF
6
and hydrogen. The second silane flow is maintained at a relatively constant flow rate that is designed to establish a tungsten nucleation film on the barrier layer. The difficulty with this approach is the potential for non-conformal tungsten deposition in the trench. At relatively high silane flow rates, tungsten may deposit at a higher rate near the top of the trench than at the bottom, resulting in a bridge-over of the trench opening and the creation of a void in the tungsten interconnect. Such voids may adversely impact the performance of the interconnect.
Another shortcoming of conventional tungsten interconnect processing stems from the highly reactive character of titanium and the chemistry associated with CVD tungsten. As noted above, many conventional CVD tungsten deposition processes involve the reduction of WF
6
in silane. This reduction process liberates quantities of fluorine which may readily diffuse into the underlying titanium based barrier film and react with the titanium therein. The incorporation of TiF
x
compounds into the adhesion layer may not only degrade the resistivity of the barrier layer, but also result in the ultimate delamination of the barrier glue layer from the underlying oxide layer. This can produce not only undesirable device performance but also catastrophic device failure depending upon the extent of the delamination.
The problem of fluorine attack may be more pronounced in circumstances where the barrier film is deliberately fabricated with a small thickness or has thickness variations due to process control issues. Device scaling frequently calls for the commensurate scaling of interconnect structures. In these circumstances, an attendant decrease in barrier film thickness is normally required if acceptable levels of interconnect resistivity are to be maintained. In addition, sometimes unavoidable process control variations in the etching of the interconnect trench may produce thin spots in the barrier film. Variations in trench topography may result in variations, including thin spots, in the thickness of the deposited barrier film. These thin spots represent areas that may be particularly susceptible to fluorine attack.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a method of fabricating a circuit device in an opening in an insulating film on a substrate is provided. The method includes forming a film of amorphous silicon and amorphous tungsten in the opening. A film of polycrystalline tungsten is formed on the film of amorphous silicon and amorphous tungsten and the substrate is annealed to react the amorphous silicon with the amorphous tungsten to form tungsten silicide on the insulating film and to increase the grain structure of the polycrystalline tungsten film.
In accordance with another aspect of the present invention, a method of fabricating a tungsten conductor structure in an opening in an oxide film on a substrate is provided that includes depositing a film of amorphous silicon and amorphous tungsten in the opening, and thereafter depositing a film of polycrystalline tungsten on the film and annealing the substrate to react the amorphous silicon with the amorphous tungsten to form tungsten silicide on the insulating film and to increase the grain structure of the polycrystalline tungsten film. The tungsten silicide film and the polycrystalline tungsten film are planarized substantially to the insulating film.
In accordance with another aspect of the present invention, a circuit device is provided that includes a substrate, an insulating film on the substrate that has an opening and a tungsten silicide film on the insulating film that has a sufficient amount of unbonded silicon to bond the tungsten silicide film to the insulating film. A tungsten film is positioned on the tungsten silicide film.
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Mi
Evans Allen
Ghatak-Roy Amiya R.
Hossain Timothy Z.
Advanced Micro Devices , Inc.
Honeycutt Timothy M.
Le Dung A
Nelms David
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