Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-04-11
2004-10-26
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000, C257S303000
Reexamination Certificate
active
06809368
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a trench top oxide (TTO) nitride liner for improved collar protection and TTO reliability in trench-capacitor vertical dynamic random access memory (DRAM) cell array devices.
2. Discussion of the Prior Art
A processing scheme employed in forming the above-described vertical DRAM cell arrays is described in detail in commonly-owned, co-pending U.S. patent application Ser. No. 09/777,576 entitled STRUCTURE AND METHOD FOR A COMPACT TRENCH-CAPACITOR DRAM CELL WITH BODY CONTACT the contents and disclosure of which are incorporated by reference as if fully set forth herein. Described now with reference to FIGS.
1
(
a
)-
1
(
f
) are the various processing steps for forming vertical DRAM cell arrays. As shown in FIG.
1
(
a
), there is depicted an initial structure that is employed in fabricating a vertical DRAM cell array. Specifically, FIG.
1
(
a
) shows an array portion of the structure that includes Si-containing substrate
10
having a material stack comprising an etch stop pad layer
12
and a hard mask
14
formed thereon. The substrate may include well regions
11
, or the well regions may be formed later in the process.
The structure shown in FIG.
1
(
a
) is made from conventional materials that are well known to those skilled in the art and conventional processes also well known in the art are employed in fabricating the same. For example, etch stop pad layer
12
may be composed of an oxide such as SiO
2
and is formed on a surface of Si-containing substrate utilizing a conventional thermal growing process and thereafter hard mask
14
, e.g., SiN, is formed on etch stop pad layer
12
by a conventional deposition process such as chemical vapor deposition (CVD), plasma-assisted CVD, sputtering, or chemical solution deposition. It should be understood that, additionally, a thick oxide layer may be formed over the SiN layer to serve as an improved hard mask during subsequent trench etching. Further, the thickness of each layer of the material stack may vary. Typically, however, the etch stop pad layer has a thickness of about 5 nm or less and the hard mask has a thickness of from about 10 to about 1000 nm.
Next, deep trenches
16
are formed in the structure shown in FIG.
1
(
a
) providing the structure shown in FIG.
1
(
b
). The term “deep trench” is used herein to denote a trench whose depth from the top surface of Si-containing substrate
10
is from about 1.0 &mgr;m or greater. The deep trenches are formed in the conventional manner of opening a trench pattern extending through the hard mask, the etch stop pad layer and a portion of the Si-containing substrate via lithography and anisotropic etching. Note deep trenches
16
, which are formed in rows and columns into the Si-containing substrate, are the areas in which the storage capacitor and vertical MOSFETs are formed.
A polysilicon buffered LOCOS (local oxidation of silicon) collar or other like collar oxide
18
is then formed in a portion of the deep trench, See FIG.
1
(
c
). Next, a capacitor (not shown in the drawings) is formed in the lower portion of the deep trench utilizing conventional processing steps well known to those skilled in the art. Included in the deep trench-processing steps is the formation of a buried plate diffusion region (not shown) and formation of node dielectric
20
about said buried plate diffusion region. As shown in FIG.
1
(
c
), node dielectric
20
extends from the lower portion of the deep trench to the upper surface of the deep trench and is formed on walls thereof. In the upper portion of the deep trench, the node dielectric serves as an etch stop layer during the formation of the buried-strap region. In the lower portion of the deep trench, the node dielectric separates the buried plate diffusion region from the deep trench conductor.
The node dielectric, which is composed of a conventional dielectric material such as a layered SiN/SiO structure, is formed by conventional processes such as thermal nitridation, CVD, plasma-assisted CVD, sputtering deposition, and the like. The deep trench is then filled with deep trench conductor
22
such as polysilicon and thereafter the deep trench conductor is recessed by conventional means to a depth which is desired for the strap (determines the channel length of the vertical MOSFET; typically of from about 100 to about 400 nm). The structure containing recessed deep trench conductor
22
is shown in FIG.
1
(
d
).
At this point of the process, a strap process, such as described in Radens, et al. “An Orthogonal 6F
2
Trench-Sidewall Vertical Device Cell for 4 Gb/16 Gb DRAM”, IEDM 2000 Tech. Dig., p. 349, is employed in forming buried-strap outdiffusion region 24; see FIG.
1
(
e
). In the exemplary structure shown in FIG.
1
(
e
), a one-sided strap (OSS) process is employed to form straps facing each other. It is understood however, that other layouts may form straps such that they do not face each other or, are on both sides of the trench. That is, other types of vertical MOSFET
3
cells may employ straps on more than a single sidewall of the trench. Note that the OSS process does not etch one of the collar oxide regions, and on that side of structure is the area in which body continuity
19
is achieved. Specifically, the buried-strap outdiffusion region is formed as follows: First, an oxide layer (not shown) is formed over the recessed deep trench conductor, followed by an etch stop liner which lines the node dielectric as well as the oxide layer previously deposited and thereafter a polysilicon placeholder material (not shown in the drawings) is formed in the upper region of the deep trench covering the exposed portions of the etch stop liner. Next, a portion of the polysilicon placeholder material on the side of the deep trench where the buried-strap is desired is etched down to the etch stop liner overlying the oxide layer at the top of the recessed conductive material.
An OSS process is then performed which may include the following processing steps: removing a portion of the polysilicon placeholder material using an etch process that is selective to the etch stop liner on a side of the deep trench where a strap is to be formed; removing the exposed collar oxide by utilizing an isotropic oxide etching process; removing portions of the etch stop liner and the node dielectric that are not protected by the remaining region of the polysilicon placeholder material; removing the remaining polysilicon placeholder material; opening a portion of the oxide layer over the deep trench polysilicon not covered by the etch stop liner; continuing the oxide etching so as to form a divot in the top collar oxide at approximately the top level of the deep trench conductor; and filling the divot with a conductive material such as doped polysilicon so as to provide a bridge between the deep trench conductor and the wall of the trench. During a subsequent annealing step, dopant from the divot filled region diffuses forming buried-strap outdiffusion region
24
. The divot filled region is labeled as
26
in the drawings. Note that on the remaining wall portion of the structure not containing buried-strap outdiffusion
24
and divot filled region
26
is an “intact” collar oxide region
18
, both directly beneath the divot filled region
26
and also on the wall not having a strap which extends all the way to the etch stop pad layer
12
. The intact collar oxide serves to electrically isolate body region
19
from trench capacitor
22
.
As is also shown in FIG.
1
(
e
), trench top oxide (TTO)
28
is formed on all horizontal surfaces including deep trench conductor
22
and divot filled collar oxide region
26
utilizing conventional deposition processes such as high-density plasma-assisted deposition and thereafter a conventional resist recess process is employed to remove the trench top oxide from top surfaces of the structure. A sacrificial oxide layer (not shown) is next formed and stripped utilizing conventional l
Divakaruni Rama
Dyer Thomas W.
Jaiprakash Venkatachalam C.
Malik Rajeev
Mandelman Jack A.
International Business Machines - Corporation
Li, Esq. Todd M. C.
Loke Steven
Scully Scott Murphy & Presser
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