TTL input buffer with on-chip reference bias regulator and decou

Details TTL input buffer with on-chip reference bias regulator and decou TTL input buffer with on-chip reference bias regulator and decou

1992-08-11

1994-12-27

Westin, Edward P.

Electronic digital logic circuitry

Interface

Logic level shifting

326112, 327546, H03K 1920

Patent

active

053768434

ABSTRACT:
An input buffer insensitive to changes in supply voltage, temperature and other operational parameters comprises a decoupling capacitor and receives a reference voltage. In one embodiment, the input buffer comprises a CMOS invertor in which a PMOS transistor is provided to decouple the output signal from a fluctuation of the ground voltage ("ground bounce"). In one embodiment, a band gap type voltage regulator provides the reference voltage of the input buffer.

REFERENCES:
patent: 4656373 (1987-04-01), Plus
patent: 4874967 (1989-10-01), Deane
patent: 4876465 (1989-10-01), Podkowa
patent: 4988897 (1991-01-01), Jeong
patent: 5057715 (1991-10-01), Larson
patent: 5214320 (1993-05-01), Truong

Affiliated with

Also associated with

Rating

TTL input buffer with on-chip reference bias regulator and decou does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with TTL input buffer with on-chip reference bias regulator and decou, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and TTL input buffer with on-chip reference bias regulator and decou will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-921061