TTL compatible hysteresis input buffer with improvable AC margin

Details TTL compatible hysteresis input buffer with improvable AC margin TTL compatible hysteresis input buffer with improvable AC margin

1990-12-19

1993-03-16

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307456, 307443, H03K 19092, H03K 19088

Patent

active

051947676

ABSTRACT:
Generally, and in one form of the invention, a circuit is provided with a terminal 50 to receive an input signal which is applied to the input of an inverter 100 which is responsive to TTL level signals and which exhibits hysteresis. The output of inverter 100 is connected to two inverter chains. The first inverter chain 110, 112, 114 is comprised of an odd number of inverters and produces a first output at terminal 62 which represents a "true" version of the input signal. The second inverter chain 102, 104, 106, 108 is comprised of an even (or zero) number of inverters and produces a second output at terminal 60 which represents a "complement" version of the input signal.

REFERENCES:
patent: 3984703 (1976-10-01), Jorgensen
patent: 4464587 (1984-08-01), Suzuki et al.
patent: 4563594 (1986-01-01), Koyama
patent: 4687954 (1987-08-01), Yasuda et al.
patent: 4779015 (1988-10-01), Erdelyi
patent: 5034623 (1991-07-01), McAdams

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