Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With stress relief
Reexamination Certificate
1999-03-17
2001-05-15
Wilczewski, Mary (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With stress relief
C257S692000, C257S702000, C438S123000
Reexamination Certificate
active
06232653
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and, more particularly, to a resin sealed package structure that is effectively adopted in such a case where a copper (alloy) type frame is used for a lead on chip (LOC) structure of an LSI circuit.
An example of the basic structure of a LOC package is shown in FIG.
16
. The basic structure of the LOC package is disclosed in JP-A-61-241959. A plurality of inner leads
3
, which are extended onto a surface of a chip with a circuit formed thereon, are fixed with an adhesive agent on the chip
5
through an insulating film. The inner leads
3
and the chip
5
are electrically connected by bonding wires (thin metallic wires)
4
In order to reduce the number of pins and to ensure stable supply of line voltage, a common inner lead
1
is provided in parallel to the arranging direction of the electrodes of the chip
5
and electrically connected, as a power lead that permits multi-point connection, by means of the chip
5
and the bonding wires
4
. Lastly, the entire assembly is sealed with a molding resin
7
. In comparison with a conventional package design wherein a chip is mounted on a die pad, the LOC design has advantages such that it permits a larger chip to be mounted, accommodates larger current to achieve higher speed, and allows higher flexibility of chip layout design.
SUMMARY OF THE INVENTION
Packages having the LOC structures usually employ alloy-42 for the lead frame constituent thereof. Using the alloy-42, which has a similar linear expansion coefficient to that of a chip, reduces the thermal mismatch in the inside of the packages, thus it is possible to design the inside of the packages in low stress during reliability tests such as a temperature cycle test. Progress has been made in the development of molding resins with lower thermal expansion, and the thermal mismatch between the alloy-42 and resins, which was a problem with conventional resin constituents, has been considerably reduced. Hence, it has become possible to provide LOC packages with high reliability.
In recent years, however, there has been an increasing trend toward larger capacities of LSI's that naturally call for larger chips, and also toward thinner packages in which the height of leads is 1.27 mm or less. This has posed the following problems. The use of frames made of alloy-42 having a large difference in coefficient of thermal linear expansion from a glass epoxy type printed circuit board has become more likely to shorten the heat cycle service life of a solder joint that electrically connects an external lead with the printed circuit board. In addition, achieving less heat resistance for the package structures has also become an important task for securing reliability in an effort to attain higher speed of LSI's and modules with higher density for larger memory capacity. There has been an increasing demand for use of copper (alloy) type frames that provide similar coefficients of thermal linear expansion to those of printed circuit boards and have good heat radiation characteristics in order to make it possible to secure reliability and to lower the heat resistance of solder joints in LOC package structures designed for DRAM's, etc. that are expected to provide larger capacities and higher speed.
When designing a package which will use a copper (alloy) type frame, there will be a significant thermal mismatch between the copper (alloy) type frame and a chip. For this reason, there has been a danger in that, during reliability tests such as a temperature cycle test, peeling may take place at the adhesive interface between the resin and an inner leads, and a common inner lead that are restrained in their thermal deformation by the chip, possibly leading to the occurrence of a package crack beginning at a peeling end of the common inner lead in particular.
FIG. 17
schematically illustrates how the package crack occurs. During a temperature cycle test or the like, the adhesive interface of a bottom surface and a side surface closer to the center of the common inner lead peel, and this is considered to lead to stress concentration on the peeling end of the common inner lead with a consequent occurrence of a crack beginning at the peeling end.
Referring now to
FIGS. 18
to
21
, a description will be given of a cause for the occurrence of the peeling of the bottom surface and the side surface closer to the center of the common inner lead.
FIGS. 18 and 19
respectively show the results of a copper frame and an alloy-42 frame in terms of stress distribution on the adhesive interface of the top surface and the bottom surface of a common inner lead that is observed during reflow soldering. It was supposed that slight initial peeling existed at one end of the adhesive interface of the common inner lead. Heating was carried out from a molding temperature (175 degrees Celsius) to 245 degrees Celsius to make finite element analysis on thermoelasticity, and the stress distributions at the initial peeling ends at that time were calculated.
It can be seen that, the, copper (alloy) type frame having a linear expansion coefficient significantly different from that of the chip develops an extremely higher shear stress in its bottom surface, where the thermal deformation of resin is restricted by the chip, than that observed in the alloy-42.
FIGS. 20 and 21
respectively show the stress distribution in the adhesive interface of the bottom surface and the side surface closer to the center of the common inner lead at room temperature after the completion of molding. As in the case shown in
FIGS. 18 and 19
, it was supposed that slight initial peeling existed at one end of the adhesive interface of the common inner lead. Cooling was carried out from a molding temperature (175 degrees Celsius) to 20 degrees Celsius to make finite element analysis on thermoelasticity, and the stress distributions at the initial peeling ends at that time were calculated. Also shown in the figures are the stress distributions in the other adhesive interface in a case where either the side surface or the bottom surface of the common inner lead peels. It can be seen that the vertical stress in the side surface of the common inner lead is three times as high as the shear stress in the bottom surface thereof. Further, if either the side surface or the bottom surface peels, the stress generated in the other interface is doubled. This means that, if either the side surface or the bottom surface peels, the possibility of peeling of the other interface will be even higher.
Accordingly, it is an object of the present invention to provide a LOC package structure capable of solving the problems discussed above when employing a copper (alloy) type frame as the lead frame constituent of a LOC package. To this end, the present invention primarily provides a configuration of a common inner lead, a thickness of resin on a chip, and a chip thickness that are effective for inhibiting the peeling of an interface of a common inner lead or for inhibiting a crack occurring at a peeling end of the common inner lead.
FIG. 22
shows an example related to a TSOP of a LOC structure employing a copper (alloy) type frame, wherein it was assumed that the bottom surface and the side surface close to the center of a common inner lead that are parallel to the arranging direction of the electrodes on a chip of the common inner lead have peeled. The common inner lead was subjected to a temperature cycle of cooling from 150 degrees Celsius to −55 degrees Celsius, and the stress intensity factors of the peeling ends of the common inner lead were calculated with respect to the thickness of resin on a chip. The conventional dimensions of the portions of the common inner lead that are parallel to the arranging direction of the electrodes on the chip complied with the specifications of the common inner lead of a TSOP having a conventional LOC structure shown in
FIG. 24
; the width was set to a minimum value, 0.3 mm, necessary for coating provided for inhibiting sho
Arita Junichi
Imura Chikako
Kohno Ryuji
Kojima Kiyomi
Miura Hideo
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Wilczewski Mary
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