Trusted computing platform

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07444601

ABSTRACT:
In a computing platform, a trusted hardware device (24) is added to the motherboard (20). The trusted hardware device (24) is configured to acquire an integrity metric, for example a hash of the BIOS memory (29), of the computing platform. The trusted hardware device (24) is tamper-resistant, difficult to forge and inaccessible to other functions of the platform. The hash can be used to convince users that that the operation of the platform (hardware or software) has not been subverted in some way, and is safe to interact with in local or remote applications.In more detail, the main processing unit (21) of the computing platform is directed to address the trusted hardware device (24), in advance of the BIOS memory, after release from ‘reset’. The trusted hardware device (24) is configured to receive memory read signals from the main processing unit (21) and, in response, return instructions, in the native language of the main processing unit (21), that instruct the main processing unit to establish the hash and return the value to be stored by the trusted hardware device (24). Since the hash is calculated in advance of any other system operations, this is a relatively strong method of verifying the integrity of the system. Once the hash has been returned, the final instruction calls the BIOS program and the system boot procedure continues as normal.Whenever a user wishes to interact with the computing platform, he first requests the integrity metric, which he compares with an authentic integrity metric that was measured by a trusted party. If the metrics are the same, the platform is verified and interactions can continue. Otherwise, interaction halts on the basis that the operation of the platform may have been subverted.

REFERENCES:
patent: 5361359 (1994-11-01), Tajalli et al.
patent: 5421006 (1995-05-01), Jablon et al.
patent: 5444850 (1995-08-01), Chang
patent: 5680547 (1997-10-01), Chang
patent: 5805712 (1998-09-01), Davis
patent: 5815665 (1998-09-01), Teper et al.
patent: 5844986 (1998-12-01), Davis
patent: 5892900 (1999-04-01), Ginter et al.
patent: 6092202 (2000-07-01), Veil et al.
patent: 6138239 (2000-10-01), Veil
patent: 6185678 (2001-02-01), Arbaugh et al.
patent: 6327652 (2001-12-01), England et al.
patent: 6330670 (2001-12-01), England et al.
patent: 6473800 (2002-10-01), Jerger et al.
patent: 6609114 (2003-08-01), Gressel et al.
patent: 2187855 (1997-06-01), None
patent: 0 421 409 (1991-04-01), None
patent: 0 510 244 (1992-10-01), None
patent: 0 825 511 (1998-02-01), None
patent: 0 848 315 (1998-06-01), None
patent: 0 849 657 (1998-06-01), None
patent: 0 893 751 (1999-01-01), None
patent: 1 026 641 (2000-08-01), None
patent: 93/25024 (1993-12-01), None
patent: 95/24696 (1995-09-01), None
patent: 97/07463 (1997-02-01), None
patent: 97/37305 (1997-10-01), None
patent: 98/15082 (1998-04-01), None
patent: 98/25372 (1998-06-01), None
patent: 98/36517 (1998-08-01), None
patent: 98/45778 (1998-10-01), None
Anderson, R. and Markus Kuhn, “Tamper Resistance—a Cautionary Note,” 16 pages, located at Internet address <www.cl.cam.ac.uk/˜mgk25/tamper.html> (1996).
Anderson, R. and Markus Kuhn, “Tamper Resistance—a Cautionary Note,”Proceedings of the Second USENIX Workshop on Electronic Commerce, Oakland CA, pp. 1-11 (Nov. 1996).
Berger, J.L., et al., “Compartmented Mode Workstation: Prototype Highlights,”IEEE Transactions on Software Engineering, vol. 16, No. 6, pp. 608-618 (Jun. 1990).
Intel, “Wired for Management Baseline specification v2.0,”Boot Integrity Services Application Programming Interface Version 1.0, 64 pages (Dec. 28, 1998).
“Information technology—Security techniques—Entity Authentication—Part 3: Mechanisms using digital signature techniques,”ISO/IEC 9798-3, 6 pages (1998).
“Information technology—Security techniques—Key management—Part 3: Mechanisms using asymmetric techniques,”ISO/IEC 11770-3, pp. 1-23 and Annexes A-E (1999).
The Trusted Computing Platform Alliance, “Building a Foundation of Trust in the PC,”, 9 pages, located at Internet address <www.trustedpc.org/home/home.html> (Jan. 2000).
Trusted Computing Platform Alliance, Main Specification Version 1.0, 284 pages (Jan. 25, 2001).
Yee, B., “Using Secure Coprocessors,” Doctoral thesis—Carnegie Mellon University, pp. 1-94 (May 1994).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Trusted computing platform does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Trusted computing platform, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Trusted computing platform will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3995869

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.