Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2004-01-22
2004-11-23
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S337000
Reexamination Certificate
active
06822290
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a Power Enhanced Drift Lateral DMOS device and more particularly to a Truncated Power Enhanced Drift Lateral DMOS device which includes a ground strap.
BACKGROUND OF THE INVENTION
Power Enhanced Drift Lateral DMOS (EDLDMOS) devices are utilized in a variety of applications.
FIG. 1
illustrates a conventional EDLDMOS device
10
. During the normal course of using a lateral DMOS device, the gate
12
is biased positively with respect to the source
14
causing a channel to be formed from source
14
across the body
16
to the drift/or drain region. The drain voltage is positive and at equal or higher voltage than the gate voltage. The source
14
and the body
16
are grounded by a diffusion of P+ to the body
16
and a metal interconnect
18
that contacts and shorts the source
14
and body
16
to ground at the point “G” shown in FIG.
1
. The reason for the grounding is to prevent snap back voltage (sustaining voltage) occurring at some low voltage below the expected operating voltage of the device. As the gate voltage is increased the current increases. The current flow through the channel region results in impact ionization occurring at the body/drift or body/drain junction. This results in electron/holes being generated. The holes move into the body (pinched and therefore it has high sheet resistance) region and flow across the body toward ground. This constitutes a current flow through the pinched and high resistance Body. The current flow results in a voltage drop along the path to the ground position. This drop is due to the current flow through the high resistance of the pinched Body. In normal operation the end of the body, marked “G”, is a distance away from the gate region. This distance we will call “x”. The body has a high sheet resistance of “Y” ohms per square from the gate region; therefore the resistance from the gate to the grounded position through the body is xY ohms. The current flow “I” across this xY resistance equates to an IR drop or voltage drop of Z volts. Under normal operation this voltage (Z) is less than +0.6 volts and therefore the NP junction drop is such that the source body junction will not be forward biased locally.
However, as the current is increased in the EDLDMOS there is an increase in the impact ionization and the hole current in the pinched body. At some point in the operation of the LDMOS, as the supply voltage is increased (increases the field at the body/drift or body/drain junction) the hole current in the body due to the increased impact ionization will increase to the point where the drop across the body resistance is such that the NP junction of the Source/Body junction will be forward biased. At this point there is an NPN bipolar transistor structure formed from the source (emitter) to body (base) to drift/drain (collector) region (see
FIG. 1
) and this device suffers a snap back of voltage similar to the LVCEO of a bipolar transistor. This is due to the high NPN beta amplifying any leakage from the drift (or drain) to body region.
In normal use this snap back (or sustaining) voltage limits the voltage of operation significantly since it occurs like a breakdown at some elevated voltage but snaps back to a much lower voltage. An example would be where the snap back voltage occurs at 30 volts but snaps back to 14 volts. The device therefore is limited to operation below this lower 14 volt level. If one were to monitor the current of the device it would be seen as current increasing dramatically and uncontrollable. This is called the sustaining current and some products state the sustaining current rather than the sustaining voltage as the limiting factor in the operation of the device. The operating current of the device must stay below this Sustaining Current level.
All designs take this into consideration and their data sheet reflects that the use of the device is limited to operation at voltages below the sustaining voltage level or currents below the sustaining current limit. Devices are designed for this to occur at an operating point outside the normal recommended operating voltage, so it is transparent to the user. The key to increasing the operating voltage level of the EDLDMOS is to make the body region (x in
FIG. 1
) of the device as short and low a resistance as possible to reduce the total resistance to ground and therefore lower the voltage drop across these regions. In this manner any current flow in the body due to impact ionization will not have an IR drop that is high enough to forward bias the source/body junction. This is not readily achievable. The prime method would be to have a short body and a solid ground tied to the source/body at the end of this short body distance. The method I will now discuss will reduce the body length to the shortest level possible (Truncated Source/Body region) while at the same time providing an absolute ground with minimal resistance. These actions will result in a higher Sustaining voltage and higher Sustaining current allowing operation of the EDLDMOS at higher power with all other structures in the device remaining unchanged.
Accordingly, what is needed is a system and method for providing a EDLDMOS device that overcomes the above-identified problems. The approach and method should be cost effective, easy to implement with existing equipment and processes and provide some technical advantages to devices within the semiconductor as well as providing a low sheet resistance interconnect. The invention discussed here addresses such needs.
SUMMARY OF THE INVENTION
A method and system for providing a Truncated Power Enhanced Drift Lateral DMOS device is disclosed. The method and system comprise providing a semiconductor substrate with a plurality of source/body structures thereon. The method and system further comprise providing a slot in the semiconductor substrate between the plurality of source/body structures to provide a truncated source; and providing a metal within the slot to provide a ground strap device.
The method and system in accordance with the present invention offers the following advantages:
1. Increases the snap back (sustaining) voltage when integrated with the EDLDMOS to the point where the device is limited by breakdown voltage of the drain/body—which is a much higher voltage than the normal snap back (sustaining) voltage.
2. Improves the gm of the device for several reasons, one of which is the fact that the device can be operated at higher current (optimum for the design where the gm peaks prior to being limited by snap back voltage) and voltage prior to being limited.
3. Reduces the capacitance of the device—drain to body capacitance is reduced due to the smaller area.
4. Reduces Ron (on resistance) due to the short and robust ground strap providing a lower source resistance than other approaches. The drain metal is also supplied in a slot which reduces any resistance, and therefore loss due to drain resistance. In addition, since the truncation allows the device to operate at higher gate voltages without suffering from limitations of current or voltage, the channel resistance is reduced which significantly reduces its contribution to Ron
5. Increases the frequency of operation due to higher gm and lower capacitance with all other conditions remaining unchanged.
6. Increases the protection against electromigration due to the heavier ground buss and improved heat transfer due to the truncation occurring via metal directly to the Silicon substrate (Ground).
7. Reduces noise that is normally generated at the source/body as it approaches snap back and due to feedback from other circuits or the power supply. Reduces noise also in the power supply lead since it is a lower resistance buss due to the thick metal buried power buss.
8. Reduces the die size since the space required for an interconnect to ground is significantly reduced and there is no isolation diffusion which takes up considerable room. The device is isolated by the ground strap oxidized slot throughout the device desig
Micrel Inc.
Nelms David
Nguyen Thinh T
Sawyer Law Group LLP
LandOfFree
Truncated power enhanced drift lateral DMOS device which... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Truncated power enhanced drift lateral DMOS device which..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Truncated power enhanced drift lateral DMOS device which... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3344622