True modulo addressing generator

Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses

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Details

711211, 711218, 711219, 711220, G06F 1202

Patent

active

060473649

ABSTRACT:
In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing a circular buffer. The address arithmetic unit includes a first selector adapted to receive as a first input a value representative of one greater than an ending address, a second input that is a beginning address, and a select input that is the sign of a displacement for stepping through addresses in a circular buffer. The first selector is adapted to select one of its inputs as an output. A carry-save adder adapted to receive as inputs an inverted representation of the first selector output, an address pointer, and a displacement. The carry-save adder is adapted to add the inputs to produce sum bits and carry bits as outputs. A sign detector adapted to determine whether a sum of the sum bits and carry bits is greater than or equal to zero, or less than zero, and for providing an output indicative of whether the sum is greater than or equal to zero, or less than zero. A second selector for receiving the comparator output and for selecting a component to include in a subsequent address pointer.

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