Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Patent
1997-02-03
1999-02-23
Santamauro, Jon
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Output switching noise reduction
326 21, 326 82, H03K 190175
Patent
active
058748334
ABSTRACT:
A true/complement integrated circuit device is disclosed for reducing an amount of simultaneous switching on a bus between a current state and a next state. The device includes a current state register connected to the bus for outputting the current state onto the bus during a first clock cycle. A next state register is provided for containing the next state, wherein the next state is a pending state of the bus intended for a next clock cycle. A comparison circuit compares a current state value in the current state register with a next state value in the next state register on a bit-by-bit basis to determine if the current state value and the next state value are of a same polarity or of an opposite polarity. A circuit is provided for determining a ratio of switching signals from an output of the bit-by-bit comparisons by the comparison circuit. The ratio determining circuit further generates a true/complement (T/C) signal having a first state if it is determined that more than a prescribed percentage of bits are in transition, the T/C signal having a second state otherwise. Lastly, a circuit is provided for complementing the bits of the next state register in response to the T/C signal being in the first state, and not complementing the bits of the next state register in response to the T/C signal being in the second state, prior to being transferred into the current state register and output onto the bus during the next clock cycle.
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Perry Patrick Edward
Ventrone Sebastian Theodore
International Business Machines - Corporation
Santamauro Jon
Walsh Robert A.
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