Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-04-11
2004-07-06
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C700S110000, C700S120000, C700S121000, C430S005000, C378S035000
Reexamination Certificate
active
06760901
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor chip manufacturing, in particular to vias, the electrical connections between successive wiring (metal) levels, and more particularly pertains to a trough adjusted optical proximity correction for dual damascene vias which takes into account the topography on a wafer created by prior wafer processing operations.
2. Discussion of the Prior Art
The via process window, for example for 0.25 &mgr;m or 0.18 &mgr;m or smaller silicon-device generations, is very small when using dual damascene integration. It is constrained by via opens in underexposed and/or negative focus conditions and via shorts in overexposed and/or positive focus conditions. The driving force behind the small via level process window is a severe topography caused by the metal level troughs. The process needs to be able to print isolated vias in very thick resist at the same time it prints densely populated or nested (e.g. an n×m array of) vias in very thin resist, as well as everything in between.
Standard optical proximity correction (OPC) examines both isolated vias and densely populated or nested (e.g. an n×m array of) vias, and ignores the topography of the wafer. The size of nested vias could be changed with a proximity correction algorithm to solve some of the problems in an attempt to make all vias print the same size. However, nested vias near the middle of a wide trough, such as bond pad vias, would also be corrected. This correction would cause the aerial image to degrade enough to make the nested vias in a wide trough disappear because they are already degraded by a focus offset induced by being in a wide trough. In other words, one problem would be fixed and another problem would be created. Since this approach is design dependent, OPC might work on one design, but not on another design.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide a trough adjusted optical proximity correction for vias which takes into account the topography on a wafer created by prior wafer processing operations, and which is applicable to all types of processes wherein a via is printed over a severe topography.
In the dual damascene process, troughs are etched into an insulating layer which can be any type of dielectric layer including an oxide layer. Vias are then printed in the troughs using photolithography. The resist used for the via lithography is not planar. It partially conforms to the topography of the wafer. This conformity of the resist to the trough topography results in the creation of many different categories of vias which do not all print with the same size, even though they are designed to be the same size. The present invention provides an optical proximity correction which takes into account the topography on a wafer created by prior wafer processing operations.
The proximity correction eliminates or reduces the possibility of nested vias in a thin resist area becoming too large and causing shorts. The adjustment of the shapes and sizes of vias pursuant to the trough adjustment of the present invention can remove or adjust the proximity correction where there is no concern for shorts and where the proximity correction could actually cause another problem. In some cases in which there is no concern about shorts, making the vias smaller in design might degrade the aerial image enough to possibly cause a via open (scummed via in resist), and hence is not a solution to the problem.
The present invention provides a solution to the via process window problem, and provides a trough adjusted optical proximity correction for vias which takes into account the topography on a wafer created by prior processing. The vias are classified into one of two groups by analyzing the via and trough designs. Coincident vias are vias which have an edge coincident with or within a specified distance of an edge of a trough, and noncoincident vias do not have an edge coincident with or within a specified distance of an edge of the trough. Any coincident via is marked as valid for an optical proximity correction (OPC).
Any noncoincident via is marked as invalid for OPC. OPC is then performed to the via level. Only vias marked as valid for OPC will keep the correction. All other vias will keep their original design size. Alternatively, coincident vias can be simply treated differently from noncoincident vias. For instance, coincident vias can be subjected to an aggressive OPC correction, while noncoincident vias are subjected to a less aggressive OPC correction.
The present invention simply makes the vias which could cause a catastrophic failure (shorts) no longer a problem, and is more reliable and effective than the prior art.
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NN8812286, “Defining Stepped Resist Structure Using E-Beam and Implemented with Proximity Correction”, IBM Technical Disclosure Bulletin, vol. 31, No. 7, pp. 286-287 (4 pages).*
Whiteside et al., Effects of Photoresist Foreshortening on an Advanced Ti/ALCu/Ti Metallurgy and W Interconnect Technology 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, Sep. 23, 1998, pp. 332-336.*
B.J. Lin, (Apr. 1985)“Depth-of-Focus Enhancement Using High Refractive Index Layer On The Imaging Layer”, vol. 27 No. 11, p. 6521.
Bergman Reuter Bette L.
Coker Eric M.
Leipold William C.
Kik Phallaka
Sabo, Esq. William D.
Scully Scott Murphy & Presser
Smith Matthew
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