Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2006-02-28
2006-02-28
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S087000, C327S112000
Reexamination Certificate
active
07005886
ABSTRACT:
A novel output driver for an integrated circuit, and method for controlling the slew rate of output signals driven by the output driver, is presented. The output driver employs a delayed activation of a succession of weak impedance zip legs followed by a preferably delayed activation of a succession of strong impedance drive legs. During a transition of an output signal on an output node of the driver from a first drive state to a second drive state, each zip leg, in its turn, turns off driving the output node to the first drive state and then turns on driving the output node to the second drive state. Once all zip legs have been activated, the activation of the succession of strong drive legs supplements the combined current provided by the zip legs to provide the full required drive current of the driver driving the output node to the second drive state.
REFERENCES:
patent: 5717342 (1998-02-01), Lotfi et al.
patent: 5977790 (1999-11-01), Sanwo et al.
patent: 6043682 (2000-03-01), Dabral et al.
patent: 6118310 (2000-09-01), Esch, Jr.
patent: 6198635 (2001-03-01), Shenoy et al.
patent: 6326802 (2001-12-01), Newman et al.
patent: 6400771 (2002-06-01), Humphrey
patent: 6448807 (2002-09-01), Ahsanullah
patent: 6509757 (2003-01-01), Humphrey
patent: 6522185 (2003-02-01), Helt et al.
patent: 6586974 (2003-07-01), Humphrey et al.
patent: 6664805 (2003-12-01), Gonzalez
patent: 6683482 (2004-01-01), Humphrey et al.
patent: 6710617 (2004-03-01), Humphrey
Shin et al., “A Slew-Rate Controlled Output Driver Using PLL as Compensation Circuit”, IEEE Journal of Solid-State Circuits, vol. 38, No. 7, pp. 1227-1233 (Jul. 2003).
Agilent Technologie,s Inc.
Chang Daniel
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