Tristate output circuit

Details Tristate output circuit Tristate output circuit

1998-11-04

2000-06-06

Tokar, Michael

Electronic digital logic circuitry

Tri-state

With field-effect transistor

325 58, 325 57, 325 26, 325 27, 325 81, 325 83, 325 86, 325 87, H03K 1900, H03K 190175

Patent

active

060723335

ABSTRACT:
The drains of P- and N-channel MOS transistors 1 and 2 are connected to each other. An output terminal is formed at the node of the drains. Each of first and second amplifier stages 4 and 5 is configured by cascading an n number of CMOS inverters. The amplifier stages drive first and second last-stage CMOS inverters 6 and 7 to drive the P- and N-channel MOS transistors 1 and 2, respectively. A dummy CMOS inverter 8 is disposed so that the input is connected to the node of the second amplifier stage 5 and the second last-stage CMOS inverter 7. The load of the second amplifier stage 5 is equal to that of the first amplifier stage 4. The drivabilities of the CMOS inverters of the same stage in the first and second amplifier stages 4 and 5 are made equal to each other. According to this configuration, the number of CMOS inverters which must be checked in a process of adjusting the duty can be reduced.

REFERENCES:
patent: 4980579 (1990-12-01), McDonald et al.
patent: 5153450 (1992-10-01), Ruetz
patent: 5448181 (1995-09-01), Chiang
patent: 5539335 (1996-07-01), Kobayashi et al.
patent: 5559464 (1996-09-01), Orii et al.
patent: 5973509 (1999-10-01), Tanigushi et al.

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