Tristate output buffer with matched signals to PMOS and NMOS...

Details Tristate output buffer with matched signals to PMOS and NMOS... Tristate output buffer with matched signals to PMOS and NMOS...

1999-12-09

2001-12-11

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Tri-state

With field-effect transistor

C326S083000, C326S057000

Reexamination Certificate

active

06329840

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to output buffers generally and, more particularly, to a method and apparatus for implementing a tristate output buffer with matched signals to PMOS and NMOS output transistors.
BACKGROUND OF THE INVENTION
When designing an output buffer, it is important to make sure that the output transistors of the buffer do not turn on at the same time. If the output transistors are on at the same time, a “rush through” current (i.e., a large amount of current pulled directly from Vcc to ground) will produce a high magnitude of noise. To avoid the “rush through” current problem, the timing of the output transistors switching must be matched to ensure that the transistors are not both in saturation at the same time.
Referring to
FIG. 1
, a diagram of a conventional approach illustrating the effects of a PMOS output transistor and an NMOS output transistor turning on at the same time is shown. If the signals A and B are not matched, the output transistors can both be on at the same time. An equivalent circuit illustrating both transistors conducting and the resulting “rush-through” currents is shown in a box
8
.
Referring to
FIG. 2
, a circuit diagram illustrating a conventional tristate output buffer
10
is shown. The output buffer
10
uses two different logic gates to generate control signals for switching the output transistors. However, matching the delay path of two different logic gates (i.e., a NAND and a NOR) is difficult.
Referring to
FIG. 3
a
, a circuit diagram of a second conventional output buffer
10
′ is shown.
FIG. 3
b
illustrates resistive and capacitive loads of the circuit
10
′ of
FIG. 3
a
. The elements in the PMOS driver path are matched through a variable resistive load (i.e., variable across process and corner variations) and associated variable load capacitances (i.e., variable since the voltage level is changing during the transition) to the variable load conditions of the NMOS driver. The turn on of one driver must be matched to the turn off of the complementary driver. In order to mach the turn on of one driver to the turn off of a complementary driver, the timing is generally altered. One conventional way to predictably alter the timing is to build a circuit with fundamentally different timing and then size the PMOS driver (i.e., 2× the value of the NMOS driver). However, for various corners and temperatures, the results of such an approach will not be consistent.
Referring to
FIG. 4
a
, a circuit diagram of a third conventional tristate output buffer
10
″ is shown.
FIG. 4
b
shows an equivalent of circuit
10
″ with tri-state off. The circuit
10
″ has similar disadvantages as the circuit
10
′.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising a first and a second circuit. The first circuit may be configured to generate a first control signal and a second control signal in response to (i) a first input signal and (ii) an enable signal. The first control signal generally matches the second control signal. The second circuit may be configured to generate a third control signal and a fourth control signal in response to (i) a second input signal and (ii) the enable signal. The third control signal generally matches the fourth control signal.
The objects, features and advantages of the present invention include providing a circuit, architecture, and method for implementing a tri-state output buffer with control signals matched to control the timing of the output transistors.


REFERENCES:
patent: 5812461 (1998-09-01), Komarek et al.
patent: 5883527 (1999-03-01), Saito
patent: 5986473 (1999-11-01), Krishnamurthy et al.
patent: 401189224-A (1989-07-01), None

Affiliated with

Also associated with

Rating

Tristate output buffer with matched signals to PMOS and NMOS... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Tristate output buffer with matched signals to PMOS and NMOS..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Tristate output buffer with matched signals to PMOS and NMOS... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2567305