Triple-well CMOS devices with increased latch-up immunity...

Details Triple-well CMOS devices with increased latch-up immunity... Triple-well CMOS devices with increased latch-up immunity...

2007-09-11

2007-09-11

Tran, Minh-Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S372000, C257SE27063, C257SE27067

Reexamination Certificate

active

11340344

ABSTRACT:
A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and forming a gap in a buried N-type doped layer formed in the P-wells, the is gap aligned under a contact to the P-well. The buried P-type doped layer and gap in the buried N-type doped layer allow a low resistance hole current path around parasitic bipolar transistors of the CMOS transistors.

REFERENCES:
patent: 5889315 (1999-03-01), Farrenkopf et al.
patent: 6927442 (2005-08-01), Kaneko et al.
patent: 2002/0063266 (2002-05-01), Lee

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