Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-04-12
2005-04-12
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C327S536000
Reexamination Certificate
active
06878981
ABSTRACT:
A charge pump stage includes a first n-channel transistor having a source coupled to an input terminal and a drain coupled to an output terminal. A second n-channel transistor has a source coupled to the input terminal, a drain coupled to a gate of the first transistor, and a gate coupled to the output terminal. A third n-channel transistor has a source coupled to the input terminal, a gate coupled to the output terminal, and a drain coupled to a p-well. A fourth n-channel transistor has a source coupled to the output terminal, a gate coupled to the input terminal, and a drain coupled to the p-well. The first, second, third and fourth transistors are fabricated in the p-well, which is surrounded by an n-well. A first capacitor is coupled to the output terminal, and a second capacitor is coupled to the gate of the first transistor.
REFERENCES:
patent: 5386151 (1995-01-01), Folmsbee
patent: 5768192 (1998-06-01), Eitan
patent: 5861772 (1999-01-01), Lee
patent: 5943271 (1999-08-01), Fujita
patent: 5973979 (1999-10-01), Chang et al.
patent: 5982224 (1999-11-01), Chung et al.
patent: 5986947 (1999-11-01), Choi et al.
patent: 6037622 (2000-03-01), Lin et al.
patent: 6191963 (2001-02-01), McPartland et al.
patent: 6198342 (2001-03-01), Kawai
patent: 6208200 (2001-03-01), Arakawa
patent: 6215348 (2001-04-01), Steensgaard-Madsen
patent: 6466489 (2002-10-01), Ieong et al.
patent: 6535052 (2003-03-01), Myono
patent: 6614699 (2003-09-01), Tanzawa
patent: 6642773 (2003-11-01), Lin et al.
patent: 6661682 (2003-12-01), Kim et al.
patent: 6674317 (2004-01-01), Chou
patent: 20010022735 (2001-09-01), Zanuccoli et al.
patent: 20020079952 (2002-06-01), Zeng et al.
patent: 20020084828 (2002-07-01), Li
patent: 20020084829 (2002-07-01), Li
patent: 20020130701 (2002-09-01), Kleveland
patent: 20020145464 (2002-10-01), Shor et al.
patent: 20020190780 (2002-12-01), Bloch
patent: 20030006825 (2003-01-01), Lee et al.
patent: 20030038670 (2003-02-01), Li
patent: 20030057469 (2003-03-01), Karaki
patent: 20030214346 (2003-11-01), Pelliconi
patent: 20040130387 (2004-07-01), Marshall
“On-Chip High-Voltage Generation in MNOS Intergrated Circuits Using a Improved Voltage Multiplier Technique”, by John F. Dickson, pp. 374-378.
“A High-Efficiency CMOS Voltage Doubler” by Pierra Favrat, et al., IEEE Journal of Solid-State Circuits, vol. 33, No. 3, Mar. 1998, pp. 410-416.
“Circuit Techniques for a 1.8-V-Only NAND Flash Memory” by Toru Tanzawa et al., IEEE Journal of Solid-State Circuits, vol. 37, No. 1, Jan. 2002, pp. 84-89.
“A 5-V-Only Operation 0.6-μm Flash EEPROM with Row Decoder Scheme in Triple-Well Structure” by Akira Umezawa et al., IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1540-1546.
Bever Hoffman & Harms LLP
Hoffman E. Eric
Le Thao X.
Pham Long
Tower Semiconductor Ltd.
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