Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-02-29
2003-10-21
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C326S011000
Reexamination Certificate
active
06637005
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to fault tolerant devices, and more particularly, to a triple redundant self-scrubbing integrated circuit.
BACKGROUND ART
Integrated circuits (IC's) used in computers and other electronic systems aboard space vehicles are susceptible to a phenomenon known as Single Event Upset, or SEU. Single Event Upset occurs when radiation passing through an integrated circuit deposits stray charges in the device, causing one of its registers to be disrupted.
One technique for reducing Single Event Upset is to encode the contents of the registers with some type of error correction. However, conventional error correction techniques require a “scrubbing” process, in which the data is frequently read out from a register, corrected, re-encoded and restored in the register. This scrub cycle interrupts the normal use of the register and, if multiple errors occur between scrub cycles, the scrubbing process may not be successful in correcting the errors.
U.S. Pat. No. 5,031,180 discloses a triple redundant fault-tolerant register. This approach has the annantage of being “self-scrubbing,” i.e., an SEU cannot force a permanent change in the state of any storage element within the register. However, implementation of this approach is more efficient with the cooperation of a semi-custom integrated circuit vendor. This is because, in order to use the method of U.S. Pat. No. 5,031,180, the invention is best designed into a semi-custom library element by an integrated circuit vendor.
The disadvantages associated with these conventional fault protection techniques have made it apparent that a new technique for protecting IC registers from Single Event Upset is needed. Preferably, the new technique is self-scrubbing. The new technique also should not require a large increase in circuit area.
SUMMARY OF THE INVENTION
It is, therefore, an object of the invention to provide an improved and reliable triple redundant self-scrubbing integrated circuit. Another object of the invention is to provide a Single Event Upset resistant device that does not require semi-custom integrated circuits.
In one embodiment of the invention, a fault tolerant integrated circuit employs triple redundant storage of data and continuous voting to protect the data from Single Event Upset, or SEU. The integrated circuit includes three or more registers and a majority voter. The three registers are connected in series to each other with the output of the first register being connected to the input of the second register and the output of the second register being connected to the input of the third register. The majority voter is connected to the output of each register and generates a signal corresponding to the majority of all of the register outputs. The output of the majority voter is connected to the input of the first register, thereby correcting any incorrect data stored the registers.
The present invention thus achieves an improved triple redundant self-scrubbing integrated circuit. The present invention is advantageous in that it does not require the generation of any new library elements, yet it is self-scrubbing.
REFERENCES:
patent: 4375683 (1983-03-01), Wensley
patent: 5031180 (1991-07-01), McIver et al.
patent: 6085350 (2000-07-01), Emmert et al.
patent: 6127864 (2000-10-01), Mavis et al.
De'cady Albert
Dooley Matthew C.
Gudmestad Terje
Hughes Electronics Corporation
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