Static information storage and retrieval – Floating gate – Particular biasing
Patent
1999-01-04
2000-04-11
Nelms, David
Static information storage and retrieval
Floating gate
Particular biasing
36518529, 36518526, G11C 1604
Patent
active
060494867
ABSTRACT:
A multiple phase method to erase data from a flash EEPROM eliminates electrical charges trapped in the tunneling oxide of a flash EEPROM to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by negative gate erasing to remove charges from the floating gate by first applying a first relatively large negative voltage pulse to the control gate. Concurrently a first moderately large positive voltage pulse is applied to the source. Also, concurrently a ground reference potential is applied to the first well and the semiconductor substrate, and the drain and second well are disconnected to allow the drain and second well to float. The flash EEPROM cell is then source erased to further remove charges from the floating gate by floating the drain and the second well and concurrently applying the ground reference potential to the semiconductor substrate, the drain, and the first well. Simultaneously, a relatively large positive voltage pulse is applied to the source. The flash EEPROM is then channel erased to detrap charges from the tunneling oxide by applying a second relatively large negative voltage pulse to the control gate of the EEPROM cell and concurrently applying a second moderately large positive voltage pulse to the first well. At this same time, a ground reference potential is applied to the semiconductor substrate and the drain, the source, and the second well are floated.
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Lee Jian-Hsing
Peng Kuo-Reay
Ackerman Stephen B.
Knowles Billy
Le Thong
Nelms David
Saile George O.
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