Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-11-30
2002-06-18
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S624000, C438S638000
Reexamination Certificate
active
06406994
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of dual damascene metallization using low dielectric constant materials in the manufacture of integrated circuits.
(2) Description of the Prior Art
The damascene or dual damascene process has become a future trend in integrated circuit manufacturing, especially in the copper metallization process. These processes are discussed in
ULSI Technology
, by Chang and Sze, The McGraw Hill Companies, Inc., NY, N.Y., c. 1996, pp. 444-445. Low dielectric constant materials have been proposed as the dielectric materials in order to reduce capacitance. In the conventional damascene scheme, one or more etch stop and/or barrier layers comprising high dielectric constant materials, such as silicon nitride, are required. This defeats the purpose of the low dielectric constant materials. It is desired to find a process which does not require a high dielectric constant etch stop/barrier layer.
U.S. Pat. No. 5,635,423 to Huang et al teaches various methods of forming a dual damascene opening. An etch stop layer such as silicon nitride or polysilicon is used. This is the conventional approach to dual damascene structure, with no consideration for dielectric constant value. U.S. Pat. Nos. 5,935,762 to Dai et al and 5,877,076 to Dai show a double mask self-aligned process using a silicon nitride etch stop layer. U.S. Pat. No. 5,798,302 to Hudson et al shows a damascene process. U.S. Pat. No. 5,741,626 to Jain et al discloses a dual damascene process using a tantalum nitride etch stop layer. U.S. Pat. No. 5,801,094 to Yew et al teaches a self-aligned process using a silicon nitride etch stop layer.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of metallization in the fabrication of integrated circuit devices.
Another object of the invention is to provide a dual damascene metallization process using low dielectric constant materials.
Yet another object of the invention is to provide a dual damascene metallization process using low dielectric constant materials without using a high dielectric constant etch stop material.
A further object of the invention is to provide a triple layered low dielectric constant material dual damascene metallization process.
In accordance with the objects of this invention a triple layered low dielectric constant material dual damascene metallization process is achieved. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first dielectric layer of a first type is deposited overlying the insulating layer. A second dielectric layer of a second type is deposited overlying the first dielectric layer. A via pattern is etched into the second dielectric layer. Thereafter, a third dielectric layer of the first type is deposited overlying the patterned second dielectric layer. Simultaneously, a trench pattern is etched into the third dielectric layer and the via pattern is etched into the first dielectric layer to complete the formation of dual damascene openings in the fabrication of an integrated circuit device. If the first type is a low dielectric constant organic material, the second type will be a low dielectric constant inorganic material. If the first type is a low dielectric constant inorganic material, the second type will be a low dielectric constant organic material.
REFERENCES:
patent: 5635423 (1997-06-01), Huang et al.
patent: 5741626 (1998-04-01), Jain et al.
patent: 5798302 (1998-08-01), Hudson et al.
patent: 5801094 (1998-09-01), Yew et al.
patent: 5877076 (1999-03-01), Dai
patent: 5935762 (1999-08-01), Dai et al.
patent: 6159845 (2000-12-01), Yew et al.
patent: 6207576 (2001-03-01), Wang et al.
patent: 6271084 (2001-08-01), Tu et al.
patent: 6281135 (2001-08-01), Han et al.
patent: 6313028 (2001-11-01), Huang et al.
patent: 6326300 (2001-12-01), Liu
patent: 6331479 (2001-12-01), Li et al.
patent: 6350675 (2002-02-01), Chooi et al.
Chang et al., “ULSI Technology”, The McGraw Hill Companies, Inc., NY, NY, c.1996, pp. 444-445.
Ang Ting Cheong
Loong Sang Yee
Quek Shyue Fong
Wong Yee Chong
Chartered Semiconductor Manufacturing Ltd.
Picardat Kevin M.
Pike Rosemary L. S.
Saile George O.
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