Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-03
2002-03-26
Tsai, Jey (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S641000, C257S640000, C438S238000, C438S563000, C438S923000, C438S783000
Reexamination Certificate
active
06362508
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits that are fabricated using advanced CMOS techniques. More specifically, the present invention relates to a structure and method used in the fabrication of CMOS memory devices.
RELATED ART
CMOS memories are widely used, for example, as flash EPROM and EEPROM memory devices. A CMOS memory cell typically includes source and drain regions diffused into a substrate and separated by a channel region, a memory structure (e.g., polysilicon) positioned on a gate oxide over the channel region, a dielectric material formed over the memory structure, and metallization formed on the dielectric that is connected to contact structures extending through vias formed in the dielectric to provide electrical connection to the source and drain regions. The dielectric material of the CMOS memory cell is referred to herein as “pre-metal” to indicate that it is formed before metallization. The CMOS memory cell is programmed/erased by charging/discharging the memory structure, thereby controlling signal currents generated in the source and drain regions.
Borophosphosilicate glass (BPSG) and Tetraethyl Orthosilicate (TEOS) undoped silicate glass are commonly used pre-metal dielectric materials in CMOS memory devices. BPSG is particularly desirable for this purpose because it can be produced with relatively high amounts of Phosphorous that helps maintain the charge stored in the underlying memory structures (i.e., memory retention).
Advanced CMOS fabrication techniques require planarization of, for example, the pre-metal dielectric using a chemical mechanical polishing (CMP) process prior to metallization to achieve adequate depth of focus during subsequent photolithography processes. However, it is difficult to achieve suitable planarization using a CMP process when a high amount of dopant (e.g., Phosphorous) is present in the pre-metal dielectric material. Therefore, a problem arises with the use of BPSG as the pre-metal dielectric material in CMOS memory devices because the low Phosphorous concentrations that are required to optimize CMP planarization produce poor memory retention characteristics, and the high Phosphorous concentrations that are required to produce optimal memory retention characteristics result in less than optimal CMP planarization.
What is needed is a pre-metal dielectric structure that provides both memory retention and facilitates CMP planarization.
SUMMARY
The present invention is directed to a triple layer pre-metal dielectric structure formed between the memory structures and the first metal layer of a CMOS memory device. The triple layer pre-metal dielectric includes a lower dielectric layer that is relatively heavily doped to provide optimal retention for the underlying memory structures, an upper dielectric layer that is relatively lightly doped to facilitate optimal CMP planarization, and an intermediate isolation layer formed between the lower and upper dielectric layers. In accordance with the present invention, the intermediate isolation layer is formed from a material that impedes the migration of dopant from the relatively heavily doped lower layer to the relatively lightly doped upper dielectric layer during, for example, heat treatment, and also impedes the migration of impurities from the upper dielectric layer to the lower layer during CMP planarization, thereby protecting the optimal memory retention characteristics of the lower dielectric layer while maintaining the optimal planarization characteristics of the upper layer throughout the fabrication process.
In accordance with a first embodiment of the present invention, both the lower and upper dielectric layers are formed using Borophosphosilicate glass (BPSG) and the intermediate isolation layer includes a Nitride layer. The concentration of Phosphorous in the BPSG of the lower dielectric layer is in the range of 7 to 9 weight percent, and the concentration of Phosphorous in the BPSG of the upper dielectric layer is in the range of 3 to 5 weight percent. In one specific embodiment, the BPSG of the lower dielectric layer includes a Boron-to-Phosphorous ratio of 3:8, while the upper dielectric layer includes a Boron-to-Phosphorous ratio of 2:4. These BPSG layers provide optimal doping concentrations in the lower and upper BPSG layers to facilitate memory retention and CMP planarization, respectively. Further, the Nitride film prevents the migration of Phosphorous from the lower BPSG layer to the upper BPSG layer during heat treatment, and prevents the migration of impurities to the lower BPSG layer that are introduced into the upper BPSG layer during CMP planarization.
In accordance with a second embodiment, upper dielectric layer is formed using Tetraethyl Orthosilicate Undoped Silicon Glass (TEOS USG). The lower dielectric layer is formed using BPSG and the intermediate isolation layer is formed using Nitride in the manner described above. The benefits of using a TEOS USG upper layer are similar to those provided above with reference to the first embodiment.
In accordance with yet another embodiment, a lower Nitride film and a lower USG layer are formed between the dielectric structure and the memory structures, thereby preventing the contamination of the memory structures.
In accordance with another embodiment of the present invention, a method of fabricating a CMOS device includes forming a memory structure on a substrate, forming a lower dielectric (e.g., BPSG) layer over the memory structure, forming an intermediate isolation layer on the lower dielectric layer, forming an upper dielectric (e.g., BPSG) layer on the intermediate isolation layer, and planarizing the upper dielectric layer using a chemical mechanical polishing process. As in the first embodiment, the lower dielectric layer has a doping concentration that is greater than that of the upper dielectric layer, thereby providing optimal memory retention and CMP planarization characteristics. Also, the intermediate isolation layer is formed by a Nitride film to prevent the migration of dopants and/or impurities between the upper and lower dielectric layers.
The novel aspects of the present invention will be more fully understood in view of the following description and drawings.
REFERENCES:
patent: 5731130 (1998-03-01), Tseng
patent: 6096654 (2000-08-01), Kirchhoff et al.
Rasovsky Michael
Shterenfeld-Lavie Zmira
Vofsi Menachem
Bever Patrick T.
Bever Hoffman & Harms LLP
Tower Semiconductor Ltd.
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