Triple latch flip flop system and method

Details Triple latch flip flop system and method Triple latch flip flop system and method

2011-01-18

2011-01-18

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S026000, C326S093000, C326S082000

Reexamination Certificate

active

07872492

ABSTRACT:
A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch.

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