Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1995-02-02
1997-10-21
Niebling, John
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
437 43, 437 52, H01L 218247, H01L 29788
Patent
active
056799705
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated EEPROM, i.e. an electrically erasable programmable read-only memory, as well as to its production process. This memory is of the flash type.
The invention more particularly applies to the field of production of integrated memory circuits of the MOS or CMOS type having high integration densities.
2. Discussion of the Background
An integrated EEPROM is an integrated circuit having a memory part formed from an array of several memory cells, which are electrically interconnected, and peripheral circuits for controlling said memory cells.
The present invention only relates to the memory part.
The concept of the flash EEPROM was introduced for the first time in 1984 by Toshiba, which proposed a triple gate structure, namely a floating gate, a control gate for programming and reading and an erasing gate made from polycrystalline silicon. This memory had a large size and, for the 2 .mu.m design rules (or floating gate width), memory cells with a surface of 64 .mu.m.sup.2. This structure was very rapidly abandoned, because it did not permit large integration dimensions, i.e. the storage of at least 10.sup.6 bits with submicron design rules.
The major development of the flash memory concept, whose main interest is high memory capacities for the replacement of hard or floppy disks in personal microcomputers, was provided in 1988 by Intel with The introduction of the so-called ETOX cell, which has the great advantage of being similar to an EPROM cell.
This cell is in particular described in IEEE Journal of Solid State Circuits, vol. 24, No. 5, October 1989, pp 1259-1263, "A 90-ns one-million erase/program cycle 1 - Mbit flash memory" by V. N. Kynett et al. Each ETOX memory cell has a single double gate transistor, whose special feature is the gate oxide thickness which is reduced to around 10 nm in order to permit an erasing by tunnel effect of the floating gate.
The programming and reading of this memory are identical to those of an EPROM. For each memory cell, erasing is carried out by transferring a voltage of 12 V to the source of the transistor, whilst maintaining its control gate at ground. The electrons of the floating Eats are collected by the source by the tunnel effect through the thin gate oxide of the cell. As the source is common no all the cells of the memory plane, erasing is collective and the entire memory can be erased in a single operation.
Therefore this means opened the way to significant integration densities and numerous companies adopted this memory cell concept. However, although this concept is very interesting from the integration density standpoint, it suffers from several problems of an electrical nature.
Thus, the use of a high voltage (12 V) on the source generally brings about the avalanching of the source-substrate junction of the cell, which leads to holes being injected into the cell gate oxide and causes electrical faults.
Moreover, the high current used during erasing requires a 12 V external supply, so that it is not possible to obtain compatibility with an external circuit supply of 5 V.
Moreover, as the thickness of the gate oxide is reduced to 10 nm or less, all the parasitic effects of an EPROM cell are amplified and are prejudicial to the operation thereof. In particular, the parasitic conduction phenomenon of cells belonging to the same line of bits as the cell being addressed (or turn-on) is increased, programming becomes more difficult and there is a significant writing of parasitic information or soft-write.
Finally, the approximately 10 nm gate oxide is subject to premature ageing due to hot electrons injected from the side of the drain during programming and the injection of hot holes during the erasing on the side of the source. Therefore said oxide ages very rapidly and it is difficult to withstand 10,000 reading-writing cycles with this memory cell type.
Recently, to get round these major problems, using the same type of memory cell, it has been proposed to supply a
REFERENCES:
patent: 5420060 (1995-05-01), Gill et al.
Solid State Technology, vol. 30, No. 10, Oct. 1987, Washington US, pp. 149-152, Lee et al., "High Speed EPROM Process Technology Development".
IEEE International Solid State Circuits Conference, vol. 28, 14 Feb. 1985, New York US, pp. 168-169, Masuoka et al., "A 256k Flash EEPROM using Triple Polysilicon Technology".
Booth Richard A.
Commissariat a l''Energie Atomique
Niebling John
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