Triple gate and double gate finFETs with different vertical...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S288000, C257S347000, C257S368000

Reexamination Certificate

active

07655989

ABSTRACT:
A semiconductor structure and its method of fabrication include multiple finFETs with different vertical dimensions for the semiconductor fins. An implant species is implanted in a bottom portion of selected semiconductor fins on which reduced vertical dimension is desired. The bottom portion of the selected semiconductor fins with implant species is etched selective to the semiconductor material without the implanted species, i.e., the semiconductor material in the top portion of the semiconductor fin and other semiconductor fins without the implanted species. FinFETs with the full vertical dimension fins and a high on-current and finFETs with reduced vertical dimension fins with a low on-current thus results on the same semiconductor substrate. By adjusting the depth of the implant species, the vertical dimension of the semiconductor fins may be adjusted in selected finFETs.

REFERENCES:
patent: 7214991 (2007-05-01), Yeo et al.
patent: 2004/0222477 (2004-11-01), Aller et al.
patent: 2005/0199919 (2005-09-01), Liu et al.
patent: 2005/0239242 (2005-10-01), Zhu et al.
Yang, Jeong-Hwan, et al., “Fully Working 1.25UM2 6T-SRAM Cell with 45nm Gate Length Triple Gate Transistors”, IEDM Tech. Dig., 2003, pp. 23-26.

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