Trinary logic input gate

Details Trinary logic input gate Trinary logic input gate

1994-12-02

1995-10-10

Westin, Edward P.

Electronic digital logic circuitry

Three or more active levels

326121, H03K 1900

Patent

active

054574110

ABSTRACT:
A trinary input logic gate (25). A first output transistor (36) is coupled to a first voltage output (V.sub.01) and pulls the voltage output to a high voltage in response to a voltage input (V.sub.IN) below a defined low threshold. A second output transistor (35) is coupled to a second voltage output (V.sub.02) and pulls the second voltage output to a low voltage in response to a voltage input above a defined high threshold. Swing limiting circuitry (28, 26) is coupled to the gates of both the first and second output transistors, and when the voltage input is between the defined thresholds, the swing limiting circuitry operates to keep the gates of the first and second output transistors within a middle range of defined thresholds such that both output transistors are enabled, and therefore the first and second voltage outputs are at opposite polarities. When the input voltage is above the high threshold, both outputs are at a low voltage. When the input voltage is below the low threshold, both outputs are at a high voltage. Thus the two voltage outputs can be used to receive and decode three distinct input states at the voltage input. The circuitry (25) is designed to provide adequate noise immunity and operate at low supply voltages, such as three volts. The circuitry is designed to be compatible with CMOS and BiCMOS digital logic semiconductor processes, and does not require additional reference voltages or any resistances. Additional embodiments are described.

REFERENCES:
patent: 4518875 (1985-05-01), Aytac
patent: 4808854 (1989-02-01), Reinagel
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patent: 5017817 (1991-05-01), Yamakawa
patent: 5132575 (1992-07-01), Chern
patent: 5198707 (1994-03-01), Nicolai
patent: 5212800 (1994-05-01), Mensch
patent: 5317211 (1994-05-01), Tang et al.
Mouftah, Design and Implementation of Three Valued Logic Systems with MOS Integrated Circuits IEE Proc. vol. 27, #4, Aug./1980.

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