Trimming algorithm for pipeline A/D converter using integrated n

Details Trimming algorithm for pipeline A/D converter using integrated n Trimming algorithm for pipeline A/D converter using integrated n

1998-11-12

2000-10-31

Wamsley, Patrick

Coded data generation or conversion

Converter calibration or testing

341118, H03M 110, H03M 106

Patent

active

061409499

ABSTRACT:
A trimming algorithm for a pipeline A/D converter includes the step of trimming the input sampling capacitor on each of the gain stages for each stage of the pipeline A/D converter. The input thereof is swept from a minimum to a maximum analog voltage and then the integral non-linearity (INL) of the A/D converter determined. The maximum transitions are then examined to determine which transitions are associated with which stage. The transitions for a given stage then constitute the gain error for these stages. The trim values are determined from this gain error and then the trim values incorporated into each of the gain stages.

REFERENCES:
patent: 5635937 (1997-06-01), Lim et al.
patent: 5712633 (1998-01-01), Bae
patent: 5861826 (1999-01-01), Shu et al.

Affiliated with

Also associated with

Rating

Trimming algorithm for pipeline A/D converter using integrated n does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Trimming algorithm for pipeline A/D converter using integrated n, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Trimming algorithm for pipeline A/D converter using integrated n will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2057165