Trilayer lift-off process for semiconductor device metallization

Details Trilayer lift-off process for semiconductor device metallization Trilayer lift-off process for semiconductor device metallization

1998-04-13

2000-12-05

Utech, Benjamin

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438708, 438717, 438723, 438725, H01L 21302

Patent

active

061566659

ABSTRACT:
The specification describes a trilevel resist technique for defining metallization patterns by lift-off. The trilevel resist comprises two standard photoresist levels separated by a thin silicon oxide layer with approximate composition SiO.sub.2.

REFERENCES:
patent: 5258264 (1993-11-01), Mathad et al.
patent: 5277749 (1994-01-01), Griffith et al.
patent: 5344517 (1994-09-01), Houlding
patent: 5360697 (1994-11-01), Mehra
patent: 5512518 (1996-04-01), Cho et al.
patent: 5541128 (1996-07-01), Kwasnick et al.

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