Trigger sequencing controller

Details Trigger sequencing controller Trigger sequencing controller

1998-02-23

2001-01-23

Iqbal, Nadeem (Department: 2785)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S030000

Reexamination Certificate

active

06178525

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to providing trigger sequencing. In particular, it relates to a single chip integrated circuit device on which trigger sequencing is implemented.
BACKGROUND TO THE INVENTION
Signals which are available at circuit board level may be monitored by logic state analyser equipment. Such logic state analyser equipment is capable of monitoring several hundred signals which might be available at the board level. Such signals may be part of the functionality, such as a memory bus, they may be signals created specifically for analysis at the board level, or they may be signals which have been brought out as external pin connections of a chip. A logic state analyser is capable of treating a particular pattern on a selected number of the signals being monitored as a trigger. It can then use this trigger to perform some action even if this is simply noting that the trigger has occurred. By allowing for several triggers, the logic state analyser is also capable of building up a complex sequence of trigger events at board level.
However the logic state analyser equipment is restricted to only monitoring board level signals and has no access to signals buried within chips.
SUMMARY OF THE INVENTION
According to the present invention there is provided a single chip integrated circuit device comprising:
on-chip functional circuitry;
a plurality of diagnostic units connected to monitor said on-chip functional circuitry to detect respective trigger conditions by comparing signals from said on-chip functional circuitry with data held in respective diagnostic registers of the diagnostic units; and
trigger sequence control circuitry arranged to receive said trigger conditions and to initiate a trigger message when a predetermined sequence of said trigger conditions is detected.
Thus, a trigger sequencing controller is integrated onto a chip together with any number of on-chip diagnostic blocks. A diagnostic block may be any unit which may be used to detect some trigger by observing a number of on-chip signals and comparing these in some manner with a register the contents of which may be programmable.
In one embodiment the functionality of the trigger sequencing controller is distributed and merged into each of a plurality of diagnostic units with a trigger bus connecting the plurality of diagnostic units. This makes a modular and easily extensible approach suitable for on-chip integration.
The trigger sequencer control circuitry is scalable, being constructed from modules, no one of which has any more control or mastership than any other, and where additional modules may be added as required.
The trigger sequence control circuitry is capable of interacting with other blocks having similar capability such that the resulting combined functionality is that of building up a complex sequence of trigger events leading to some resultant trigger event which is used for some diagnostic purpose.
The trigger sequence control circuitry may comprise a plurality of distributed circuits associated respectively with certain diagnostic circuits and connected to a common trigger bus.
One of said diagnostic units may be a breakpoint unit which holds the breakpoint address and which is operable to issue a signal to interrupt normal operation of the CPU when a next instruction which should be executed by the CPU matches the breakpoint address.
One of the diagnostic units may be a breakpoint range unit which has first and second breakpoint registers for holding respectively upper and lower breakpoint addresses between which normal operation of the CPU may be interrupted, the breakpoint range unit being operable to issue a breakpoint signal to interrupt the normal operation of the CPU when the next instruction to be executed lies between the lower and upper breakpoint addresses.
The diagnostic unit may comprise an instruction trace controller operable to monitor addresses to be executed by the CPU and to cause selected ones of said addresses to be stored at trace storage locations dependent on discontinuities in said addresses.
For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings.


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