Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-12-26
2006-12-26
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07155694
ABSTRACT:
In accordance with a method for generating a trial placement plan for an IC having two or more identical modules, a floor plan reserves a separate area of identical size and shape for each of the identical modules, one of which is designated a “master module” and the others designated “clone modules”. A placement and routing (P&R) tool initially places all of the cell instances of the clone modules at the center of their reserved areas. The P&R tool then employs a conventional placement algorithm to iteratively adjust positions of cell instances of all other modules, including the master module within their reserved areas in a manner that tries to minimize net lengths. The P&R tool copies the placement within the master module area into the clone module areas either after every N>0 iterations of the placement algorithm and/or after the placement algorithm has completed placement for the master module area.
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Chen Hsi-Chuan
Eichenseer Patrick J.
Huang Dennis
Cadence Design Systems Inc.
Kik Phallaka
Rosenberg , Klein & Lee
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