Tri-stating output buffer during initialization of...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition

Reexamination Certificate

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Details

C711S103000, C711S105000, C711S154000, C711S166000, C711S167000, C710S010000

Reexamination Certificate

active

06938117

ABSTRACT:
A synchronous memory device that avoids erroneous output while internal initialization is taking place. In one embodiment, a tri-state logic circuit is used to selectively tri-state an output buffer during memory initialization. The output buffer is used to output data from a memory array to DQ lines. Tri-stating the output buffer floats the DQ lines. Thus, data in the DQ lines is not output in response to commands. Control circuitry signals the tri-state logic circuit to tri-state the output buffer during initialization. In another embodiment, an external processor can be used to provide a read status command to the memory to determine the status of memory initialization. In this embodiment, tri-stating the output buffer during initialization is momentarily overridden to respond to the read status command.

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