Electronic digital logic circuitry – Tri-state – With field-effect transistor
Patent
1997-06-09
2000-11-28
Tokar, Michael
Electronic digital logic circuitry
Tri-state
With field-effect transistor
326 83, 326 56, 326 57, 36523008, H03K 1900, H03K 1902
Patent
active
061540560
ABSTRACT:
An address buffer for a memory device comprises a tri-state input stage, an address output latch, and an inverter that are successively coupled. In one embodiment, the address buffer uses address enable signals for controlling both the tri-state input stage and the address output latch. In another embodiment, the tri-state input stage includes series coupled pairs of N and P channel transistors. The address signal is provided to gates of one P channel and one N channel transistor which form an inverter. The other two transistors have their gates coupled to the address enable signal and its complement for enabling the tri-state input stage. In another embodiment, the address output latch includes a multiplexed feedback loop that is controlled by the address enable signal and its complement. A method of operating the buffer comprises sampling a signal. The sampled signal is inverted. The inverted sampled signal is latched. Finally, the latched signal is inverted. The sampling and latching steps occur mutually exclusively.
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Micro)n Technology, Inc.
Tan Vibol
Tokar Michael
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