Tri-state input detection circuit

Details Tri-state input detection circuit Tri-state input detection circuit

1998-11-25

2000-10-17

Tokar, Michael

Electronic digital logic circuitry

Tri-state

326 60, H03K 1900, H03K 1902

Patent

active

061337536

ABSTRACT:
A tri-state input detection circuit produces two binary outputs that indicate whether a tri-state input signal is high, low, or in a hi-impedance state. A pair of transistors conduct a current in response to a tri-state signal presented at an input node. Circuitry is provided to pull the input node to a known voltage when the input signal is in its hi-Z state. The transistors are series-connected to respective current sources, with the junctions between the transistors and their current sources forming the circuit's binary outputs. The output impedances of the current sources are made less than those of their respective transistors, so that when turned on by the input signal, a transistor pulls its associated output high or low. The circuit produces a unique binary output for each of the three input signal states. In a preferred embodiment, sampling pulses briefly activate the circuit, and downstream circuitry latches the circuit's outputs, reducing current consumption to zero except during the sampling period.

REFERENCES:
patent: 4100429 (1978-07-01), Adachi
patent: 4449065 (1984-05-01), Davies, Jr.
patent: 4465944 (1984-08-01), Shin
patent: 5194766 (1993-03-01), Sugawara
patent: 5598110 (1997-01-01), Chang
patent: 5714892 (1998-02-01), Bowers et al.

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