Tri-state bus contention circuit preventing false switching caus

Details Tri-state bus contention circuit preventing false switching caus Tri-state bus contention circuit preventing false switching caus

1998-03-31

2000-10-17

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710131, 710107, 326 82, G06F 1340

Patent

active

061346209

ABSTRACT:
A method of avoiding contention on a communications bus using an improved tri-state driver, which negates one of the internal driver signals during a restore region of the driver cycle, such that the driver cannot switch to the high state when there is poor synchronization that delays one of the internal driver signals. Restoring logic provides a first logic signal and a second logic signal. An input gate is asserted to an active level in response to the first logic signal, and gating logic conditionally enables the input gate in response to the second signal.

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