Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-06-15
2001-08-28
Hoang, Huan (Department: 2818)
Electronic digital logic circuitry
Interface
Current driving
C326S087000, C326S024000
Reexamination Certificate
active
06281708
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a tri-state bus structure. In particular, the present invention relates to a tri-state bus amplifier-accelerator for driving long and heavily loaded busses.
2. Discussion of the Related Art
Bus structures for carrying data or control signals are generally long and connected to and through a significant number of circuits and subsystems. Thus, capacitance associated with such bus structures are appreciable. Careful design of such bus structures is necessary to ensure performance.
In a conventional integrated circuit, size of a bus driver increases with the length, load, and speed of a bus. However, the size of a bus driver cannot increase without limitations. First, the silicon area required for a large driver is significant. In addition, multiple levels of pre-drivers are necessary to provide a large bus driver, leading to further requirements in silicon area. Furthermore, a long bus has a long propagation delay.
Bus design has thus an adverse feedback problem—i.e., a bus having a large number of drivers and receivers has a large capacitance, thus requiring larger drivers, which in turn further increases the capacitance, requiring still larger drivers and incurring further pre-driver delays.
One source of capacitance is the parasitic capacitance of a transistor. The drive of a transistor increases linearly with its channel width, which also increases parasitic capacitance.
What is needed is a bus structure that does not require progressively larger drivers for additional load. Furthermore, what is needed is a driver structure that minimizes the driver size as well as the propagation delays.
SUMMARY OF THE INVENTION
The present invention provides a centralized amplifier-accelerator for a tri-state bus structure and an associated method to drive long and heavily loaded busses. This central amplifier-accelerator includes a sense circuit which detects voltage transition at the N-channel threshold for rising transitions or at the P-channel threshold for falling transitions. Once the sense circuit detects a transition, the amplifier-accelerator is triggered to drive the output driver which switches the bus.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.
REFERENCES:
patent: 4482824 (1984-11-01), Tzeng
patent: 5272368 (1993-12-01), Turner et al.
patent: 5936895 (1999-08-01), Shirley
Hoang Huan
Kwok Edward C.
National Semiconductor Corporation
Skjerven Morrill & MacPherson LLP
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