Tri-state buffer circuit

Details Tri-state buffer circuit Tri-state buffer circuit

1986-03-28

1988-02-16

Heinz, A. J.

Static information storage and retrieval

Systems using particular element

Ternary

365177, 307473, 357 43, G11C 1134, G11C 1156, G11C 700, H01L 2702

Patent

active

047259825

ABSTRACT:
A tri-state buffer circuit according to the present invention comprises a switching circuit connected to an input terminal (IN), tri-state and inverted tri-state input terminals (T, T), and a first power supply terminal for generating first and second switching signals (A, B) which have a first and second levels, respectively, only when the tri-state signal is on a first level, regardless the level of the input signal; an inverter circuit connected to said switching circuit, and the first power supply terminal for inverting the first switching signal (A) from said switching circuit as an output signal; a selection circuit connected to said switching circuit and inverter circuit for maintaining a signal, which have a second level, equal to the inverted signal only when the tri-state signal is on first level; a first type bipolar transistor whose base is connected to said inverter circuit, whose collecter is connected to the first power supply terminal, and whose emitter is connected to the output terminal of the tri-state circuit; and a first type bipolar transister whose base is connected to said selection circuit, whose collecter is connected to the output terminal of the tri-state circuit, and whose emitter is connected to a second power supply terminal.

REFERENCES:
patent: 3602733 (1971-08-01), Aoki
patent: 4280065 (1981-07-01), Minato et al.
patent: 4380709 (1983-04-01), Au
W. J. Scarpero, Jr., "Field-Effect Transistor Bidirectional Driver Control Circuit", IBM Technical Disclosure Bulletin, vol. 16, No. 8, Jan. 1984, p. 2442.
Patent Abstracts of Japan, vol. 2, No. 112(E-78)(6086), Sep. 16, 1978; & JP-A-53 76 719, Jul. 7, 1978 (Fujitsu K.K.).

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