Tri-level segmented control transistor and fabrication method

Details Tri-level segmented control transistor and fabrication method Tri-level segmented control transistor and fabrication method

1998-04-07

2003-12-09

Mintel, William (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S344000, C257S408000, C257S900000, C438S306000

Reexamination Certificate

active

06661057

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to semiconductor integrated circuit device structures and associated methods of fabrication. More particularly, the invention pertains to tri-level control transistors having segmented control gates.
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate electrode to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the channel being doped with a conductivity type opposite the conductivity type of the source and drain. The gate electrode is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate electrode, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, the source and drain are formed by introducing dopants of a second conductivity type (P or N) into the semiconductor substrate of a first conductivity type (N or P) using a patterned gate electrode as a mask. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate electrode and the source/drain regions.
Polysilicon (also called polycrystalline silicon, polysilicon-Si or polysilicon) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon as the gate electrode in place of aluminum. Since polysilicon has the same high melting point as a silicon substrate, it can be deposited prior to source and drain formation, and serve as a mask during introduction of the source and drain regions by ion implantation. The resistance of polysilicon can be further reduced by forming a silicide on its top surface.
There is a relentless trend to miniaturize semiconductor dimensions. The number of IGFETs that can be manufactured on an integrated circuit chip can be increased by decreasing the horizontal dimensions. Resolution refers to the horizontal linewidth or space that a lithographic system can adequately print or resolve. Lithographic systems include optical projection and step and repeat equipment, and electron beam lithography equipment. In optical systems, for instance, resolution is limited by the equipment (e.g., diffraction of light, lens aberrations, mechanical stability), optical properties of the photoresist (e.g., resolution, photosensitivity, index of refraction), and process characteristics (e.g., softbake step, develop step, postbake step, and etching step).
Furthermore, scaling down the horizontal dimensions generally is attained by a corresponding decrease in the vertical dimensions. As IGFET vertical dimensions are reduced and the supply voltage remains nearly constant (e.g., 3V), the maximum channel electric field &egr;
ymax
near the drain tends to increase. If the electric field becomes strong enough, so-called hot-carrier effects may occur. For instance, hot electrons can overcome the potential energy barrier between the substrate and the gate insulator thereby causing hot carriers to become injected into the gate insulator. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage of the device.
A number of techniques have been utilized to reduce hot carrier effects. One such technique is a lightly doped drain (LDD). The LDD reduces hot carrier effects by reducing the maximum channel electric field &egr;
ymax
. Reducing the electric field on the order of 30-40% can reduce hot-electron-induced currents by several orders of magnitude. The drain is typically formed by two ion implants. A light implant is self-aligned to the gate electrode, and a heavy implant is self-aligned to the gate electrode on which sidewall spacers have been formed. The spacers are typically oxides or nitrides. The purpose of the lighter first dose is to form a lightly doped region of the drain (or LDD) at the edge near the channel. The second heavier dose forms a low resistivity region of the drain, which is subsequently merged with the lightly doped region. Since the heavily doped region is farther away from the channel than a conventional drain structure, the depth of the heavily doped region can be made somewhat greater without adversely affecting the device characteristics. The lightly doped region is not necessary for the source (unless bidirectional current is used), however LDD structures are typically formed for both the source and drain to avoid the need for an additional masking step.
Disadvantages of LDDs are their increased fabrication complexity compared to conventional drain structures, and parasitic resistance. LDDs exhibit relatively high parasitic resistance due to their light doping levels. During operation, the LDD parasitic resistance can decrease drain current, which in turn may reduce the speed of the IGFET.
In the manufacture of integrated circuits, the planarization of semiconductor wafers is becoming increasingly important as the number of layers used to form integrated circuits increases. For instance, the gate electrode and/or metallization layers formed to provide interconnects between various devices may result in nonuniform surfaces. The surface nonuniformities may interfere with the optical resolution of subsequent lithographic steps, leading to difficulty with printing high resolution patterns. The surface nonuniformities may also interfere with step coverage of subsequently deposited metal layers and possibly cause open circuits.
Accordingly, a need exists for an IGFET that can be manufactured with reduced horizontal dimensions, that preferably includes an LDD with reduced parasitic resistance as well as a substantially planar top surface. It is especially desirable that the IGFET have a channel length that can be significantly smaller than the minimum resolution of the available lithographic system.
SUMMARY OF THE INVENTION
A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor.
In accordance with an embodiment of a method for fabricating a transistor, lightly doped source and drain (LDD) regions are formed aligned to a gate electrode. After forming an insulating layer adjacent the exposed surfaces of the gate electrode, conductive spacers are formed disposed overlying the LDD regions. These spacers are electrically isolated from the gate electrode by the insulating layer. Heavily doped source and drain (S/D) regions are formed which are aligned to the spacers and make electrical contact, for example through a salicide process, supplied to the conductive spacer, the gate electrode, and the S/D regions. The described structure advantageously supplies dynamic control of the channel region through dynamic, independent control of the LDD portions of the S/D regions.
In some embodiments, the tri-level control transistors are controlled to have a gate electrode modify the drain potential of a transistor. In still other embodiments, the tri-level control transistors allow independent bias of the main gate electrode and source/drain regions. Independently biasing the gate electrode and source/drain regions permits precise control of transistor performance to improve transistor reliability and enhance operating speed.
Many advantages are attained by the described semiconductor integrated circuit and associated fabrication method. The semiconductor integrated circuit attains a reduced surface area through active area isolation by shallow trench isolation (STI) and electrical contacts formed to S/D regions within the STI region.


REFERENCES:
patent: 4868617 (1989-09-01), Chiao et al.
patent: 4951100 (1990-08-01), Parillo
patent: 5091763 (1992-02-01), Sanchez
pa

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