Tri-layered power scheme for architectures which contain a...

Details Tri-layered power scheme for architectures which contain a... Tri-layered power scheme for architectures which contain a...

2011-03-01

2011-03-01

Stoynov, Stefan (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S320000, C713S324000, C455S574000, C365S227000

Reexamination Certificate

active

07900072

ABSTRACT:
Various embodiments are directed to a tri-layered power scheme for architectures which contain a microcontroller. In one embodiment, a power management system may comprise a microcontroller in a chipset, a low consumption power well to control a power supply to the microcontroller, and a power controller to control a power supply to the low consumption power well. The power management system may be arranged to switch among multiple power consumption states. In a maximum power consumption state, the microcontroller is on, the power controller is on, and the low consumption power well is on. In an intermediate power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is required to be on. In a minimum power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is optionally on or off at the discretion of the power controller. Other embodiments are described and claimed.

REFERENCES:
patent: 6904533 (2005-06-01), Kuo et al.
patent: 7421591 (2008-09-01), Sultenfuss et al.
patent: 7596687 (2009-09-01), Sultenfuss et al.
patent: 2009/0021450 (2009-01-01), Heller et al.

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