Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-02-07
2001-06-05
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S701000, C438S713000, C438S640000, C438S978000
Reexamination Certificate
active
06242344
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating small geometry dual-damascene structures.
(2) Description of the Prior Art
In fabricating very and ultra large scale integration (VLSI and ULSI) circuits, one of the more important aspects of this fabrication is the fabrication of metal interconnect lines and vias that provide the interconnection of integrated circuits in semiconductor devices. The invention specifically addresses the fabrication of conductive lines and vias using the damascene process. Using the dual damascene process, an insulating layer or a dielectric layer, such as silicon oxide, is patterned with a multiplicity of openings for the conductive lines and vias. The openings are simultaneously filled with a metal, such as aluminum, and serve to interconnect the active and/or the passive elements of an integrated circuit. The dual damascene process is also used for forming multilevel conductive lines of metal, such as copper, in the insulating layers, such as polyimide, of multilayer substrates on which semiconductor devices are mounted. Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, conductive via openings also are formed. Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating processing steps. The dual damascene process requires two masking steps to form first the via pattern after which the pattern for the conductive lines is formed.
In the standard dual damascene process an insulating layer is deposited over the surface of a substrate and coated with a layer of photoresist, the photoresist is exposed through a via mask which contains an image pattern of the via openings. The via pattern is anisotropically etched in the upper half of the insulating layer. The photoresist now is exposed through an interconnect line pattern mask with an image pattern of conductive line openings. The second exposure of the interconnecting line patterns is aligned with the via mask pattern to encompass the via openings. In anisotropically etching the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched and replicated in the lower half of the insulating material. After the etching is complete, both the vias and line openings are filled with metal. The metal is now polished back to form an inlaid planar dual damascene structure.
Critical to a good dual damascene structure is that the edges of the via openings in the lower half of the insulating layer are clearly defined. Furthermore, the alignment of the two masks is critical to assure that the pattern for the conductive lines aligns with the pattern of the vias. This requires a relatively large tolerance while the via may not extend over the full width of the conductive line.
Semiconductor device performance improvements are largely achieved by reducing device dimensions while increasing device-packaging densities. One of the major technologies that is used in the creation of semiconductor devices is photolithography. Photolithography is used to project images of device features that are contained in a reticle onto the surface where these images have to be created as device features. To obtain the required image quality and the subsequent high device yield, the images that are created in this manner must be precise and easy to repeat. This requirement of image precision brings with it that the light that is used to project the images is not deflected before reaching its target surface and not reflected upon reaching its target surface. Reflection of the projected light can occur if metal surfaces are underlying the target surface and if these metal surfaces readily reflect light. Unwanted reflections that are created by underlying layers of reflective materials are a prime source of distortion in the patterns that are created by photolithographic patterning.
To minimize the effect that reflected light has on image creation, Anti Reflective Coatings (ARC's) have been developed. These ARC's are frequently applied as a blanket deposition over the surface that caused light reflection such as a layer of metal. The coating of ARC however is an electrically conductive coating and can therefore only be applied where the application of this coating does not cause electrical short circuits between the layers over which the ARC is deposited. To prevent electrical short circuits from occurring, the ARC must be removed from between electrically conducting device features. This poses a problem for applications where dual damascene structures are being created. In the standard dual damascene process, an insulating layer is deposited over a semiconductor surface and coated with a layer of photoresist, the photoresist is exposed through a via mask with contains an image pattern of the via openings. The via pattern is anisotropically etched in the upper half of the insulating layer. The photoresist now is exposed through an interconnect line pattern mask with an image pattern of conductive line openings. The second exposure of the interconnecting line patterns is aligned with the via mask pattern to encompass the via openings. In anisotropically etching the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched and replicated in the lower half of the insulating material. After the etching is complete, both the vias and line openings are filled with metal. The metal is now polished back to form an inlaid planar dual damascene structure. The metal that is used to fill the dual damascene structure is never etched meaning that no layer of ARC can be deposited over the dual damascene structures since this would cause massive electrical shorts between the dual damascene structures through the layer of ARC.
The solution to the problem of electrical shorts that are created through the deposited layer of ARC is to find materials that have ARC properties that however are not electrically conductive, such as a typical dielectric material. Some dielectric ARC's, such as silicon-rich silicon nitride or aluminum nitride, are known in the art. These dielectric ARC's however prove to be not suited for use as anti reflecting coatings because these materials exhibit the combination of ARC and insulating properties only at light frequencies in the Deep Ultra Violet (248 nm) wavelength range. For most of the photolithographic exposures that are applied in the creation of small geometry device-size features, such as I-line or G-line processing, these exposures are made in the higher wavelength (near ultra-violet or NUV with a wavelength of 365 nm) where the optimal ARC characteristics of these materials are not present.
In the formation of semiconductor metal lines and via or contact openings, the metal must be patterned. Photolithography is a common approach wherein patterned layers are usually formed by spinning on a layer of photoresist, projecting light through a photomask with the desired pattern onto the photoresist to expose the photoresist to the pattern, developing the photoresist, washing off the undeveloped photoresist, and plasma etching to clean out the areas where the photoresist has been washed away. The exposed resist may be rendered insoluble (negative working) and form the pattern, or soluble (positive working) and be washed away. In either case, the remaining resist on the surface forms the desired pattern.
In the ideal world of creating semiconductor devices, such semiconductor fabrication aspects as layer depositions (for instance the deposition of a layer of
Cheng Tsun-Lung Alex
Koh Leong Tee
Sajan Marokkey Raphael
Xie Joseph Zhifeng
Ackerman Stephen B.
Chaudhari Chandra
Institute of Microelectronics
Nguyen Thanh
Saile George O.
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