Tri-gate patterning using dual layer gate stack

Details Tri-gate patterning using dual layer gate stack Tri-gate patterning using dual layer gate stack

2007-12-28

2010-06-29

Monbleau, Davienne (Department: 2893)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S283000, C257SE21409

Reexamination Certificate

active

07745270

ABSTRACT:
In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker than the first, is created over the n-diffusion fin. A silicon germanium layer is formed over the first and second work function metal layers. A polysilicon layer is formed over the silicon germanium layer and is polished. The polysilicon layer over the first work function metal layer is thicker than the polysilicon layer over the second work function metal layer. A hard mask is patterned and used to etch the polysilicon layer and the silicon germanium layer to create gate stacks. The etch rate of the silicon germanium layer is faster over the first work function metal layer.

REFERENCES:
patent: 7314789 (2008-01-01), Cabral et al.
patent: 7358121 (2008-04-01), Chau et al.
patent: 7528025 (2009-05-01), Brask et al.

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