Tri-gate integration with embedded floating body memory cell...

Details Tri-gate integration with embedded floating body memory cell... Tri-gate integration with embedded floating body memory cell...

2011-06-28

2011-06-28

Pham, Thanhha (Department: 2894)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S283000, C257SE21623

Reexamination Certificate

active

07968392

ABSTRACT:
Dual-gate memory cells and tri-gate CMOS devices are integrated on a common substrate. A plurality of silicon bodies are formed from a monocrystalline silicon on the substrate to define a plurality of transistors including dual-gate memory cells, PMOS transistors, and NMOS transistors. An insulative layer is formed overlying the silicon body of the memory cell. A layer of a high-k dielectric and at least a metal layer cover the silicon bodies and their overlying layers. Next, gain regions of the transistors are filled with polysilicon. Thus, a gate is formed on the top surface and both sidewalls of a tri-gate transistor. Thereafter, the high-k dielectric and the metal layer overlying the insulative layer of the memory cell are removed to expose the insulative layer. Thus, two electrically-isolated gates of the memory cell are formed.

REFERENCES:
patent: 6835614 (2004-12-01), Hanafi et al.

Affiliated with

Also associated with

Rating

Tri-gate integration with embedded floating body memory cell... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Tri-gate integration with embedded floating body memory cell..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Tri-gate integration with embedded floating body memory cell... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2688129