Trenched DMOS transistor with buried layer for reduced on-resist

Details Trenched DMOS transistor with buried layer for reduced on-resist Trenched DMOS transistor with buried layer for reduced on-resist

1995-08-21

1997-05-13

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257334, H01L 2910

Patent

active

056295430

ABSTRACT:
A trench DMOS transistor includes a buried layer region formed between the drain region and overlying drift region and having a doping type the same as that of the drift region and drain region. The buried layer region is more highly doped than the drain region or drift regions and is formed by e.g. implantation prior to epitaxial growth of the overlying drift region. By providing an optimized doping profile for the buried layer region, it is ensured that avalanche breakdown occurs at the buried layer region/body region. Thus drain-source on resistance is reduced because the JFET region present in prior art devices is eliminated, while device ruggedness and reliability are enhanced.

REFERENCES:
patent: 5034785 (1991-07-01), Blanchard
patent: 5298442 (1994-03-01), Bulucea et al.
patent: 5341011 (1994-08-01), Hshieh et al.
patent: 5410170 (1995-04-01), Bulucea et al.
patent: 5473176 (1995-12-01), Kakumoto

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